On the design of single-inductor multiple-output DC-DC buck converters

Abstract – Design techniques for single inductor multiple output (SIMO) DC-DC buck converters are presented. The suitable control of a multiple feedback loop enables the sharing of a single inductor with many outputs with a good stability and limited cross regulation. The method has been verified with simulations at the behavioural and transistor level to obtain four independent regulated output voltages ranging from 0 V to 1 V below the power supply voltage. The use of a suitable analog processing of errors allows obtaining a power efficiency as high as 86%. I

Development of Efficient Soft Switching Synchronous Buck Converter Topologies for Low Voltage High Current Applications

Switched mode power supplies (SMPS) have emerged as the popular candidate in all the power processing applications. The demand is soaring to design high power density converters. For reducing the size, weight, it is imperative to channelize the power at high switching frequency. High switching frequency converters insist upon soft switching techniques to curtail the switching losses. Several soft switching topologies have been evolved in the recent years. Nowadays, the soft switching converters are vastly applied modules and the demand is increasing for high power density and high efficiency modules by minimizing the conduction and switching losses. These modules are generally observed in many applications such as laptops, desktop processors for the enhancement of the battery life time. Apart from these applications, solar and spacecraft applications demand is increasing progressively for stressless and more efficient modules for maximizing the storage capacity which inturn enhances the power density that improves the battery life to supply in the uneven times. Modern trends in the consumer electronic market focus increases in the demand of lower voltage supplies. Conduction losses are significantly reduced by synchronous rectifiers i.e., MOSFET’s are essentially used in many of the low voltage power supplies. Active and passive auxiliary circuits are used in tandem with synchronous rectifier to diminish the crucial loss i.e., switching loss and also it minimizes the voltage and current stresses of the semiconductor devices. The rapid progress in the technology and emerging portable applications poses serious challenges to power supply design engineers for an efficient power converter design at high power density. The primary aim is to design and develop high efficiency, high power density topologies like: buck, synchronous buck and multiphase buck converters with the integration of soft switching techniques to minimize conduction and switching losses sustaining the voltage and current stresses within the tolerable range. In this work, two ZVT-ZCT PWM synchronous buck converters are introduced, one with active auxiliary circuit and the other one with passive auxiliary circuit. The operating principle and comprehensive steady state analysis of the ZVT-ZCT PWM synchronous buck converters are presented. The converters are designed to have high efficiency and low voltage that is suitable for high power density application. The semiconductor devices used in the topologies in addition to the main switch operate with soft switching conditions. The viii Abstract topologies proposed render a large overall efficiency in contrast to the contemporary topologies. In addition the circuit’s size is less, reliable and have high performance-cost ratio. The new generation microprocessor demands the features such as low voltage, high current, high power density and high efficiency etc., in the design of power supplies. The supply voltage for the future generation microprocessors must be low, in order to decrease the power consumption. The voltage levels are dripping to a level even less than 0.7V, and the power consumption increases as there is an increase in the current requirement for the processor. In order to meet the demands of the new generation microprocessor power supply, a soft switching multiphase PWM synchronous buck converter is proposed. The losses in the proposed topology due to increasing components are pared down by the proposed soft switching technique. The proposed converters in this research work are precisely described by the mathematical modelling and their operational modes. The practicality of the proposed converters for different applications is authenticated by their simulation and experimental results

Analysis of Buck Converters for On-Chip Integration With a Dual Supply Voltage Microprocessor

Sweely, “Building and using a highly parallel programmable logi

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Scalable Analysis, Verification and Design of IC Power Delivery

Due to recent aggressive process scaling into the nanometer regime, power delivery network design faces many challenges that set more stringent and specific requirements to the EDA tools. For example, from the perspective of analysis, simulation efficiency for large grids must be improved and the entire network with off-chip models and nonlinear devices should be able to be analyzed. Gated power delivery networks have multiple on/off operating conditions that need to be fully verified against the design requirements. Good power delivery network designs not only have to save the wiring resources for signal routing, but also need to have the optimal parameters assigned to various system components such as decaps, voltage regulators and converters. This dissertation presents new methodologies to address these challenging problems. At first, a novel parallel partitioning-based approach which provides a flexible network partitioning scheme using locality is proposed for power grid static analysis. In addition, a fast CPU-GPU combined analysis engine that adopts a boundary-relaxation method to encompass several simulation strategies is developed to simulate power delivery networks with off-chip models and active circuits. These two proposed analysis approaches can achieve scalable simulation runtime. Then, for gated power delivery networks, the challenge brought by the large verification space is addressed by developing a strategy that efficiently identifies a number of candidates for the worst-case operating condition. The computation complexity is reduced from O(2^N) to O(N). At last, motivated by a proposed two-level hierarchical optimization, this dissertation presents a novel locality-driven partitioning scheme to facilitate divide-and-conquer-based scalable wire sizing for large power delivery networks. Simultaneous sizing of multiple partitions is allowed which leads to substantial runtime improvement. Moreover, the electric interactions between active regulators/converters and passive networks and their influences on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level co-design of a complete power delivery network is facilitated by an automatic optimization flow. Results show significant performance enhancement brought by the co-design

Custom Silicon for Low-Cost Information Dissemination among Illiterate People Groups.

In this work, we present an Information and Communications Technology (ICT) device that improves the quality of life of the poorest people in the world by enabling information access through Very Large Scale Integrated chips. Identified as agrarian farmers that subsist on less than $2 a day, the world’s poorest people face many challenges that make developing an ICT device difficult. We argue that prior devices do not adequately overcome the unique problems of: cost, power, connectivity, usability, robustness, and illiteracy. We show that while many of these constraints need to be addressed, cost represents the greatest fundamental challenge to widespread use and adoption of ICT devices. To address this challenge, this thesis presents a custom silicon chip design referred to as “Literacy in Technology” (LIT). LIT enables an audio computer ICT device to overcome the constraints through a number of techniques: A high level of integration of the components on a single die reduces its cost and form-factor. LIT’s power management system ensures long lifetime through energy consumption reduction by exploiting unique characteristics of Carbon-Zinc batteries, common in the developing world. Its Hybrid Switch Capacitor Network addresses off-chip component cost by using only inexpensive capacitors, further reducing cost. LIT’s unique memory hierarchy, a large on-chip cache backed directly by NAND Flash combined with a simple and low area core, reduces cost by not requiring DRAM or NOR Flash. LIT’s power-on-reset and brown-out-detection overcomes Carbon-Zinc battery’s high hysteresis resulting in higher robustness. LIT further reduces cost through overloading the functionality of PCB traces as both a human input interface and as information transfer from device to device. We show how LIT and its unique solutions allow us to develop an ICT device targeted towards developing regions at a total estimated electronics cost of less than$6. Furthermore, LIT reduces recurring costs through lowered energy consumption and increased robustness when compared to previous ICT devices. Although many of our novel technical contributions were motivated by strong price elasticity in developing regions, the techniques developed are equally applicable to rugged, low-power systems targeted at mainstream applications.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102429/1/zhiyoong_1.pd

Development of Improved Performance Switchmode Converters for Critical Load Applications

Emerging portable applications and the rapid advancement of technology have posed rigorous challenges to power engineers for an efficient power delivery at high power density. The foremost objectives are to develop high efficiency, high power density topologies such as: buck, synchronous buck and multiphase buck converters, with the implementation of soft switching technology to reduce switching losses maintaining voltage and current stresses within the permissible range. Demand of low voltage power supply for telecom system leads to narrow duty cycle which compels to increase operating switching frequency. Design of conventional buck converter under narrow duty cycle is quite objectionable since it leads to poor utilization of components as well as it degrades the system efficiency. A high switching frequency operation reduces the switch conduction time that leads to large increase in switching losses and increases the control complexity. Therefore, duty cycle has to be extended and at the same time switching losses have to be minimized. Transformer based topology can be used to extend the duty cycle. But to reduce switching losses soft switching techniques should be implemented. An isolated buck converter with simple clamp capacitor scheme is proposed to reduce switching losses and to extend duty cycle by optimizing the turn ratio. Extended duty cycle impose limit on dead time. Dead time has to be controlled with respect to duty cycle to reduce body diode conduction loss and to avoid the shoot through conditions in our proposed topology. The proposed clamp capacitor scheme control the dead time as well as provide better efficiency with reduction in switching losses maintaining ripples within the allowable range

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance

Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies

Control of Switched Mode Power Supplies (SMPS) has been traditionally achieved through analog means with dedicated integrated circuits (ICs). However, as power systems are becoming increasingly complex, the classical concept of control has gradually evolved into the more general problem of power management, demanding functionalities that are hardly achievable in analog controllers. The high flexibility offered by digital controllers and their capability to implement sophisticated control strategies, together with the programmability of controller parameters, make digital control very attractive as an option for improving the features of dcdc converters. On the other side, digital controllers find their major weak point in the achievable dynamic performances of the closed loop system. Indeed, analogto-digital conversion times, computational delays and sampling-related delays strongly limit the small signal closed loop bandwidth of a digitally controlled SMPS. Quantization effects set other severe constraints not known to analog solutions. For these reasons, intensive scientific research activity is addressing the problem of making digital compensator stronger competitors against their analog counterparts in terms of achievable performances. In a wide range of applications, dcdc converters with high efficiency over the whole range of their load values are required. Integrated digital controllers for Switching Mode Power Supplies are gaining growing interest, since it has been shown the feasibility of digital controller ICs specifically developed for high frequency switching converters. One very interesting potential benefit is the use of autotuning of controller parameters (on-line controllers), so that the dynamic response can be set at the software level, independently of output capacitor filters, component variations and ageing. These kind of algorithms are able to identify the output filter configuration (system identification) and then automatically compute the best compensator gains to adjust system margins and bandwidth. In order to be an interesting solution, however, the self-tuning should satisfy two important requirements: it should not heavily affect converter operation under nominal condition and it should be based on a simple and robust algorithm whose complexity does not require a significant increase of the silicon area of the IC controller. The first issue is avoided performing the system identification (SI) with the system open loop configuration, where perturbations can be induced in the system before the start up. Much more challenging is to satisfy this requirement during steady state operations, where perturbations on the output voltage are limited by the regular operations of the converter. The main advantage of steady state SI methods, is the detection of possible non-idealities occurring during the converter operations. In this way, the system dynamics can be consequently adjusted with the compensator parameters tuning. The resource saving issue, requires the development of äd-hocßelf-tuning techniques specifically tailored for integrated digitally controlled converters. Considering the flexibility of digital control, self-tuning algorithms can be studied and easily integrated at hardware level into closed loop SMPS reducing development time and R & D costs. The work of this dissertation finds its origin in this context. Smart power management is accomplished by tuning the controller parameters accordingly to the identified converter configuration. Themain difficult for self-tuning techniques is the identification of the converter output filter configuration. Two novel system identification techniques have been validated in this dissertation. The open loop SI method is based on the system step response, while dithering amplification effects are exploited for the steady state SI method. The open loop method can be used as autotunig approach during or before the system start up, a step evolving reference voltage has been used as system perturbation and to obtain the output filter information with the Power Spectral Density (PSD) computation of the system step response. The use of ¢§ modulator is largely increasing in digital control feedback. During the steady state, the finite resolution introduces quantization effects on the signal path causing low frequency contributes of the digital control word. Through oversampling-dithering capabilities of ¢§ modulators, resolution improvements are obtained. The presented steady state identification techniques demonstrates that, amplifying the dithering effects on the signal path, the output filter information can be obtained on the digital side by processing with the PSD computation the perturbed output voltage. The amount of noise added on the output voltage does not affect the converter operations, mathematical considerations have been addressed and then justified both with a Matlab/Simulink fixed-point and a FPGA-based closed loop system. The load output filter identification of both algorithms, refer to the frequency domain. When the respective perturbations occurs, the system response is observed on the digital side and processed with the PSD computation. The extracted parameters are the resonant frequency ans the possible ESR (Effective Series Resistance) contributes,which can be detected as maximumin the PSD output. The SI methods have been validated for different configurations of buck converters on a fixed-point closed loop model, however, they can be easily applied to further converter configurations. The steady state method has been successfully integrated into a FPGA-based prototype for digitally controlled buck converters, that integrates a PSD computer needed for the load parameters identification. At this purpose, a novel VHDL-coded full-scalable hybrid processor for Constant Geometry FFT (CG-FFT) computation has been designed and integrated into the PSD computation system. The processor is based on a variation of the conventional algorithm used for FFT, which is the Constant-Geometry FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can achieve improved logic saving by trading off with computational speed. The pipelined architecture is composed of a number of stages equal to the number of PEs and achieves the highest possible throughput, at the expense of more hardware usage