Analysis and design of high-transconductance RF mosfet voltage to-current converters

The research described in this thesis is concerned with analysis and design of "HighTransconductance RF MOSFET Voltage-to-Current (V-I) Converters". Various V-I converter circuits published in the past have been reviewed by the author in order to understand the different techniques employed to improve transconductance (Gt), linear operating range and total harmonic distortion (THO). Throughout this research, the emphasis has been to improve the above mentioned parameters. All the V-I converter circuits reported have been simulated using PSPICE and the results compared with the values obtained by theoretical analysis. Some of the results of this work have been already reported by the author in the technical literature. (See Chapter 9, at the end of this thesis, where reference to two publications by the author is given.) It was essential to obtain accurate CMOS device parameters values, such as Early Voltage, transconductance parameter ratios!! (gm/gds), X (gmbl'gm) and inter-electrode capacitances, to facilitate the design the prQcess. This was achieved using an extensive set of simulations for the transistor operating under different bias conditions. Furthermore, a measurement technique, thought to be novel, for the direct determination of the transconductance ratios!! and X is proposed. In the next part of the work several types of current mirror are compared against the standard current mirrors, using analytical and simulation methods. Furthermore several MOSFET V-I converter designs were critically reviewed to understand the various existing techniques and their limitations. Two novel techniques, Drain-Source Feedback Circuits (DSFCs) and Drain-Gate Feedback Circuits (OGFCs) ere implemented with a new temperature-compensation scheme, designed to operate well in an industrial environment (-40°C - +8S°C). It is found that the best types of V -I converters were the DSFCs which, offer a more accurate value of Gt (3.386mS) and the THO less than -S7dB for a differential input operating range SOOm V at 1 GHz with a 3V total rail voltage. The OGFC circuits were also meet the initial design targets, the value of THO is less then -SOdB, and operating in the Giga hertz frequency range is possible. Preliminary investigation on future work shows promising results

Chemical Current-Conveyor: a new approach in biochemical computation

Biochemical sensors that are low cost, small in size and compatible with integrated circuit technology play an essential part in the drive towards personalised healthcare and the research described in this thesis is concerned with this area of medical instrumentation. A new biochemical measurement system able to sense key properties of biochemical fluids is presented. This new integrated circuit biochemical sensor, called the Chemical Current-Conveyor, uses the ion sensitive field effect transistor as the input sensor combined with the current-conveyor, an analog building-block, to produce a range of measurement systems. The concept of the Chemical Current-Conveyor is presented together with the design and subsequent fabrication of a demonstrator integrated circuit built on conventional 0.35μm CMOS silicon technology. The silicon area of the Chemical Current-Conveyor is (92μm x 172μm) for the N-channel version and (99μm x 165μm) for the P-channel version. Power consumption for the N-channel version is 30μW and 43μW for the P-channel version with a full load of 1MΩ. The maximum sensitivity achieved for pH measurement was 46mV per pH. The potential of the Chemical Current Conveyor as a versatile biochemical integrated circuit, able to produce output information in an appropriate form for direct clinical use has been confirmed by applications including measurement of (i) pH, (ii) buffer index ( ), (iii) urea, (iv) creatinine and (v) urea:creatinine ratio. In all five cases the device has been demonstrated successfully, confirming the validity of the original aim of this research project, namely to produce a versatile and flexible analog circuit for many biochemical measurement applications. Finally, the thesis closes with discussion of another potential application area for the Chemical Current Conveyor and the main contributions can be summarised by the design and development of the first: ISFET based current-conveyor biochemical sensor, called 'Chemical Current Conveyor, CCCII+' has been designed and developed. It is a general purpose biochemical analog building-block for several biochemical measurements. Real-time buffer capacity measurement system, based on the CCCII+, which exploits the imbedded analog computation capability of the CCCII+. Real-time enzyme based CCCII+ namely, Creatinine-CCCII+ and Urea-CCCII+ for real-time monitoring system of renal system. The system can provide outputs of 3 important parameters of the renal system, namely (i) urea concentration, (ii) creatinine concentration, and (ii) urea to creatinine ratio

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Modeling and design of an active silicon cochlea

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references.Silicon cochleas are inspired by the biological cochlea and perform efficient spectrum analysis: They realize a bank of constant-Q Nth-order filters with O(N) efficiency rather than O(N²) efficiency due to their use of an exponentially tapered filter cascade. They are useful in speech-recognition front ends, cochlear implants, and hearing aids, especially as architectures for improving spectral analysis in noisy environments and for performing low-power spectrum analysis. In this thesis I describe four contributions towards improving the state-of-the-art in silicon-cochlea design, two of which involve theoretical modeling, and two of which involve integrated-circuit design. On the theoretical side, I first show that a simple rational approximation to distributed partition impedances in the biological cochlea captures its essential features and enables an efficient artificial implementation achieving maximum gain in a minimum number of stages while still maintaining stability. In particular, I show that the terminating impedance of the cochlea is crucial for its stability and discuss various analytic methods for termination. Second, I derive a novel composite artificial cochlear architecture composed of a cascade of all-pass second-order filters from a first-principles analysis of the biological cochlear transmission line. The novel all-pass architecture reduces phase lag and group delay in the silicon cochlea, a problem in prior designs, sharpens its high-frequency rolloff slopes, increases its frequency selectivity, and improves its nonlinear compression characteristics. On the circuit side, I first present a novel current-mode log-domain topology that simultaneously increases signal-to-noise ratio (SNR) and dynamic range while lowering power consumption in resonant filters with high quality factor Q.(cont.) The novel topology is validated in a second-order low-pass resonant filter, which is employed in the silicon cochlea, demonstrating a reduction in power consumption and increase in SNR by a factor of Q. When bias currents in the filter are adjusted as the signal level varies, this technique enables an improvement in maximum SNR by a factor of Q and an increase in maximum non-distorted signal power and dynamic range by a factor of Q⁴. Measurements from a chip in a 0.18-[mu]m 1.1-V CMOS technology achieve a quiescent power consumption of 580-nW at a 15-kHz center frequency with a maximum SNR of 41.3dB and dynamic range of 76dB for a Q=4. Finally, I describe a current-mode -stage 0.18-[mu]m silicon cochlea that achieves 79dB of dynamic range with 41-[mu]W power consumption on a 1-V power supply over a usable 3.5kHz-14kHz frequency range. These numbers represent an 18dB improvement in dynamic range and a 12.5x reduction in power consumption over prior state-of-the-art silicon cochleas.by Serhii M. Zhak.Ph.D

Electronic transport in single-walled carbon nanotubes, and their application as scanning probe microscopy tips

Single-walled carbon nanotubes (SWNTs) are remarkable molecules composed of a graphite sheet rolled into a seamless cylinder. With nanometer diameter, and micrometer length, their physical properties are due to a mixture of quantum and classical effects. This work investigates the electrical transport properties of these molecules, and demonstrates their application as Atomic Force Microscopy (AFM) tips. SWNTs were grown by catalysed chemical vapour deposition (cCVD), and characterized using AFM, electron microscopy and Raman spectroscopy. Electronic devices were fabricated from SWNTs grown by cCVD on Si02. Electronic transport through the SWNT devices was studied using electric force microscopy (EFM) and scanned gate microscopy (SGM). SGM was used to study the effects of defects on transport through the devices. A novel form of SGM, based on the modulation of the tip-gating potential by the oscillating tip in dynamic mode AFM, was demonstrated and shown to massively enhance the signal to noise ratio. Using EFM we directly demonstrated the transition from ballistic transport in metallic SWNT at low source-drain voltages, to diffusive transport at high-source drain voltages. EFM was also used to image the charge injection induced around a SWNT at high gate voltages, and correlate it with the observed hysteresis in the transconductance of SWNT devices. Both of these results are of fundamental importance to the future applications of SWNT electronic devices. The high bias behaviour of metallic SWNT is crucial to their proposed use as interconnects in nanoscale devices. Hysteresis in the transconductance of semiconducting SWNT devices is limiting their application as chemical and biological sensors, where environmental effects are monitored by the change in conductance of the devices. SWNTs were mounted at the apex of AFM tips, and used as high resolution scanning probe tips. Electrical transport through the SWNT-AFM tips was investigated using both liquid (Hg) and solid contacts. An efficient technique for fabricating nanowire AFM tips, using SWNT-AFM tips as templates, was also invented. The resultant nanowire tips were shown to be robust, high aspect ratio, electrical probes. Using calibration samples fabricated from SWNTs, SWNT-AFM tips were quantitatively demonstrated to increase the resolution of EFM. Under optimal conditions identical features could be distinguished down to separations as low as 15 nm, comparable to the topographic resolution

Design et test pour la haute performance d'un convertisseur A/D basé sur l'architecture "subranging"

Les architectures des convertisseurs A/N -- Un nouveau A/n pour des applications à haute résolution et haute vitesse -- Un commutateur actif en mode courant pour des applications de hautes performances à faibles tensions -- Un nouveau convertisseur A/N "subranging" en mode courant pour des applications à haute vitesse -- Un nouveau BIST numérique intégré pour convertisseurs analogique-numérique