66 research outputs found

    Time-Sensitive Networking for Industrial Automation: Challenges, Opportunities, and Directions

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    With the introduction of Cyber-Physical Systems (CPS) and Internet of Things (IoT) into industrial applications, industrial automation is undergoing tremendous change, especially with regard to improving efficiency and reducing the cost of products. Industrial automation applications are often required to transmit time- and safety-critical data to monitor and control industrial processes, especially for critical control systems. There are a number of solutions to meet these requirements (e.g., priority-based real-time schedules and closed-loop feedback control systems). However, due to their different processing capabilities (e.g., in the end devices and network switches), different vendors may come out with distinct solutions, and this makes the large-scale integration of devices from different vendors difficult or impossible. IEEE 802.1 Time-Sensitive Networking (TSN) is a standardization group formed to enhance and optimize the IEEE 802.1 network standards, especially for Ethernet-based networks. These solutions can be evolved and adapted into a cross-industry scenario, such as a large-scale distributed industrial plant, which requires multiple industrial entities working collaboratively. This paper provides a comprehensive review on the current advances in TSN standards for industrial automation. We present the state-of-the-art IEEE TSN standards and discuss the opportunities and challenges when integrating each protocol into the industry domains. Finally, we discuss some promising research about applying the TSN technology to industrial automation applications

    Real-time analysis of MPI programs for NoC-based many-cores using time division multiplexing

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    Worst-case execution time (WCET) analysis is crucial for designing hard real-time systems. While the WCET of tasks in a single core system can be upper bounded in isolation, the tasks in a many-core system are subject to shared memory interferences which impose high overestimation of the WCET bounds. However, many-core-based massively parallel applications will enter the area of real-time systems in the years ahead. Explicit message-passing and a clear separation of computation and communication facilitates WCET analysis for those programs. A standard programming model for message-based communication is the message passing interface (MPI). It provides an application independent interface for different standard communication operations (e.g. broadcast, gather, ...). Thereby, it uses efficient communication patterns with deterministic behaviour. In applying these known structures, we target to provide a WCET analysis for communication that is reusable for different applications if the communication is executed on the same underlying platform. Hence, the analysis must be performed once per hardware platform and can be reused afterwards with only adapting several parameters such as the number of nodes participating in that communication. Typically, the processing elements of many-core platforms are connected via a Network-on-Chip (NoC) and apply techniques such as time-division multiplexing (TDM) to provide guaranteed services for the network. Hence, the hardware and the applied technique for guaranteed service needs to facilitate this reusability of the analysis as well. In this work we review different general-purpose TDM schedules that enable a WCET approximation independent of the placement of tasks on processing elements of a many-core which uses a NoC with torus topology. Furthermore, we provide two new schedules that show a similar performance as the state-of-the-art schedules but additionally serve situations where the presented state-of-the-art schedules perform poorly. Based on these schedules a procedure for the WCET analysis of the communication patterns used in MPI is proposed. Finally, we show how to apply the results of the analysis to calculate the WCET upper bound for a complete MPI program. Detailed insights in the performance of the applied TDM schedules are provided by comparing the schedules to each other in terms of timing. Additionally, we discuss the exhibited timing of the general-purpose schedules compared to a state-of-the-art application specific TDM schedule to put in relation both types of schedules. We apply the proposed procedure to several standard types of communication provided in MPI and compare different patterns that are used to implement a specific communication. Our evaluation investigates the communications’ building blocks of the timing bounds and shows the tremendous impact of choosing the appropriate communication pattern. Finally, a case study demonstrates the application of the presented procedure to a complete MPI program. With the method proposed in this work it is possible to perform a reusable WCET timing analysis for the communication in a NoC that is independent of the placement of tasks on the chip. Moreover, as the applied schedules are not optimized for a specific application but can be used for all applications in the same way, there are only marginal changes in the timing of the communication when the software is adapted or updated. Thus, there is no need to perform the timing analysis from scratch in such cases

    CarRing IV- Real-time Computer Network

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    Ob in der Automobil-, Avionik- oder Automatisierungstechnik, die Fortschritte in der Echtzeitkommunikation richten sich auf weitere Verbesserungen bereits existierender Lösungen. Im Kfz-Bereich führen die steigenden Zahlen computerbasierter Systeme, Anwendungen und Anschlüsse sowie die Verwendung mehrerer proprietärer Kommunikationsstandards zu einem immer komplexeren Kabelbaum. Ursächlich hierfür sind inkompatible Standards, wodurch nicht nur die Kosten, sondern auch das Gewicht und damit der Kraftstoffverbrauch negativ beeinflusst werden. Im ersten Teil der Dissertation wird das Echtzeitprotokoll von CarRing IV (CRIV) vorgestellt. Es bietet isochrone und harte Echtzeitgarantien, ohne dass eine netzwerkweite Synchronisation erforderlich ist. Mit bis zu 16 Knoten pro Ring kann ein CR-IV-Netz aus bis zu 256 Ringen bestehen, die durch Router miteinander verbunden sind. CR-IV verwendet ein reduziertes OSI-Modell (Schichten 1-3, 7), das für seine Anwendungsbereiche sowohl typisch als auch vorteilhaft ist. Außerdem unterstützt es sowohl ereignis- als auch zeitgesteuerte Kommunikationsparadigmen. Der Transparent-Modus ermöglicht es CR-IV, als Backbone für bestehende Netze zu verwenden, wodurch Inkompatibilitätsprobleme beseitigt werden und der Wechsel zu einer einheitlicheren Netzlösung erleichtert wird. Mit dieser Funktionalität können Nutzergeräte über ein CR-IV-Netz miteinander verbunden werden, ohne dass der Nutzer eingreifen oder etwas ändern muss. Durch Multicast unterstützt CRIV auch die Emulation von Feldbussen. Der zweite Teil der Dissertation stellt den anderen wichtigen Aspekt von CR-IV vor. Alle Schichten des OSI-Modells sind in einem FPGA mit Hardware Description Languages (HDLs) ohne Hard- oder Softprozessoren implementiert. Das Register-Transfer-Level (RTL)-Hardwaredesign von CR-IV wird mit einem neuen Ansatz erstellt, der am besten als tokenbasierter Datenfluss beschrieben werden kann. Der Ansatz ist sowohl vertikal als auch horizontal skalierbar. Er verwendet lose gekoppelte Processing Elements (PEs), die stateless arbeiten, sowie Arbiter/Speicherzuordnungspaare. Durch die granulare Kontrolle und die Aufteilung aller Aspekte einer Lösung eignet sich der Ansatz für die Implementierung anderer Software-Level-Lösungen in Hardware. Viele Testszenarios werden durchgeführt, um die in CR-IV erzielten Ergebnisse zu verdeutlichen und zu überprüfen. Diese Szenarien reichen von direkten Leistungsmessungen bis hin zu verhaltensspezifischen Tests. Zusätzlich wird eine Labor-Demo erstellt, die grundsätzlich auf ein Proof of Concept zielt. Die Demo stellt einen praktischen Test anstelle szenariospezifischer Tests dar. Alle Testszenarien und die Labor-Demo werden mit den Prototyp-Boards des Projekts durchgef¨uhrt, d.h. es sind keine Simulationstests. Die Ergebnisse stellen die realistischen Leistungen von CR-IV mit bis zu 13,61 Gbit/s dar.Whether be it automotive, avionics or automation, advances in their respective real-time communication technology focus on further improving preexisting solutions. For in-vehicle communication, the ever-increasing number of computer-based systems, applications and connections as well as the use of multiple proprietary communication standards results in an increasingly complex wiring harness. This is in-part due to those standards being incompatible with one another. In addition to cost, this also impacts weight, which in turn affects fuel consumption. The work presented in this thesis is in-part theoretical and in-part applied. The former is represented by a new protocol, while the latter corresponds to the protocol’s hardware implementation. In the first part of the thesis, the real-time communication protocol of CarRing IV (CR-IV) is presented. It provides isochronous and hard real-time guarantees without requiring network-wide clock synchronization. With up to 16 nodes per ring, a CR-IV network can consist of as many as 256 rings interconnected by routers. CR-IV uses a reduced OSI model (layers 1-3, 7), which is both typical of and preferable for its application areas. Moreover, it supports both event- and time-triggered communication paradigms. The transparent mode feature allows CR-IV to act as a backbone for existing networks, thereby addressing incompatibility concerns and easing the transition into a more unified network solution. Using this feature, user devices can communicate with one another via a CR-IV network without requiring user interference, or any user device or application changes. Combined with the protocol’s reliable multicast, the feature extends CR-IV’s capabilities to include field bus emulation. The second part of the thesis presents the other important aspect of CR-IV. All of its OSI model layers are implemented in a FPGA using Hardware Description Languages (HDLs) without relying-on or including any hard or soft processors. CR-IV’s Register-Transfer Level (RTL) hardware design is created using a new approach that can best be described as token-based data-flow. The approach is both vertically and horizontally scalable. It uses stateless and loosely coupled Processing Elements (PEs) as well as arbiter/memory allocation pairs. By having granular control and compartmentalizing every aspect of a solution, the approach lends itself to being used for implementing other software-level solutions in hardware. Many test scenarios are conducted to both highlight and examine the results achieved in CR-IV. Those scenarios range from direct performance measurements to behavior-specific tests. Moreover, a lab-demo is created that essentially amounts to a proof of concept. The demo represents a practical test as opposed to a scenariospecific one. Whether be it test scenarios or the lab-demo, all are carried-out using the project’s prototype boards, i.e. no simulation tests. The results obtained represent CR-IV’s real-world realistic outcomes with up to 13.61 Gbps

    MACHINE LEARNING IN THE DESIGN SPACE EXPLORATION OF TSN NETWORKS

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    Real-time systems are systems that have specific timing requirements. They are critical systems that play an important role in modern societies, be it for instance control systems in factories or automotives. In recent years, Ethernet has been increasingly adopted as layer 2 protocol in real-time systems. Indeed, the adoption of Ethernet provides many benefits, including COTS and cost-effective components, high data rates and flexible topology. The main drawback of Ethernet is that it does not offer "out-of-the-box" mechanisms to guarantee timing and reliability constraints. This is the reason why time-sensitive networking (TSN) mechanisms have been introduced to provide Quality-of-Service (QoS) on top of Ethernet and satisfy the requirements of real-time communication in critical systems. The promise of Ethernet TSN is the possibility to use a single network for different criticality levels, e.g, critical control traffic and infotainment traffic sharing the same network resources. This thesis is about the design of Ethernet TSN networks, and specifically about techniques that help quantify the extent to which a network can support current and future communication needs. The context of this work is the increasing use of design-space exploration (DSE) in the industry to master the complexity of designing (e.g. in terms of architectural and technological choices) and configuring a TSN network. One of the main steps in DSE is performing schedulability analysis to conclude about the feasibility of a network configuration, i.e., whether all traffic streams satisfy their timing constraints. This step can take weeks of computations for a large set of candidate solutions with the simplest TSN mechanisms, while more complicated TSN mechanisms will require even longer time. This thesis explores the use of Artificial Intelligence (AI) techniques to assist in the design of TSN networks by speeding up the DSE. Specifically, the thesis proposes the use of machine learning (ML) as an alternative approach to schedulability analysis. The application of ML involves two steps. In the first step, ML algorithms are trained with a large set of TSN configurations labeled as feasible or non-feasible. Due to its pattern recognition ability, ML algorithms can predict the feasibility of unseen configurations with a good accuracy. Importantly, the execution time of an ML model is only a fraction of conventional schedulability analysis and remains constant whatever the complexity of the network configurations. Several contributions make up the body of the thesis. In the first contribution, we observe that the topology and the traffic of a TSN network can be used to derive simple features that are relevant to the network feasibility. Therefore, standard and simple machine learning (ML) algorithms such as k-Nearest Neighbors are used to take these features as inputs and predict the feasibility of TSN networks. This study suggests that ML algorithms can provide a viable alternative to conventional schedulability analysis due to fast execution time and high prediction accuracy. A hybrid approach combining ML and schedulability analyses is also introduced to control the prediction uncertainty. In the next studies, we aim at further automating the feasibility prediction of TSN networks with the Graph Neural Network (GNN) model. GNN takes as inputs the raw data from the TSN configurations and encodes them as graphs. Synthetic features are generated by GNN, thus the manual feature selection step is eliminated. More importantly, the GNN model can generalize to a wide range of topologies and traffic patterns, in contrast to the standard ML algorithms tested before that can only work with a fixed topology. An ensemble of individual GNN models shows high prediction accuracies on many test cases containing realistic automotive topologies. We also explore possibilities to improve the performance of GNN with more advanced deep learning techniques. In particular, semi-supervised learning and self-supervised learning are experimented. Although these learning paradigms provide modest improvements, we consider them promising techniques due to the ability to leverage the massive amount of unlabeled training data. While this thesis focuses on the feasibility prediction of TSN configurations, AI techniques have huge potentials to automate other tasks in real-time systems. A natural follow-up work of this thesis is to apply GNN to multiple TSN mechanisms and predict which mechanism can provide the best scheduling solution for a given configuration. Although we need distinct ML models for each TSN mechanism, this research direction is promising as TSN mechanisms may share similar feasibility features and thus transfer learning techniques can be applied to facilitate the training process. Furthermore, GNN can be used as a core block in deep reinforcement learning to find the feasible priority assignment of TSN configurations. This thesis aims to make a contribution towards DSE of TSN networks with AI

    The Virtual Bus: A Network Architecture Designed to Support Modular-Redundant Distributed Periodic Real-Time Control Systems

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    The Virtual Bus network architecture uses physical layer switching and a combination of space- and time-division multiplexing to link segments of a partial mesh network together on schedule to temporarily form contention-free multi-hop, multi-drop simplex signalling paths, or 'virtual buses'. Network resources are scheduled and routed by a dynamic distributed resource allocation mechanism with self-forming and self-healing characteristics. Multiple virtual buses can coexist simultaneously in a single network, as the resources allocated to each bus are orthogonal in either space or time. The Virtual Bus architecture achieves deterministic delivery times for time-sensitive traffic over multi-hop partial mesh networks by employing true line-speed switching; delays of around 15ns at each switching point are demonstrated experimentally, and further reductions in switching delays are shown to be achievable. Virtual buses are inherently multicast, with delivery skew across multiple destinations proportional to the difference in equivalent physical length to each destination. The Virtual Bus architecture is not a purely theoretical concept; a small research platform has been constructed for development, testing and demonstration purposes

    Timing in Technischen Sicherheitsanforderungen für Systementwürfe mit heterogenen Kritikalitätsanforderungen

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    Traditionally, timing requirements as (technical) safety requirements have been avoided through clever functional designs. New vehicle automation concepts and other applications, however, make this harder or even impossible and challenge design automation for cyber-physical systems to provide a solution. This thesis takes upon this challenge by introducing cross-layer dependency analysis to relate timing dependencies in the bounded execution time (BET) model to the functional model of the artifact. In doing so, the analysis is able to reveal where timing dependencies may violate freedom from interference requirements on the functional layer and other intermediate model layers. For design automation this leaves the challenge how such dependencies are avoided or at least be bounded such that the design is feasible: The results are synthesis strategies for implementation requirements and a system-level placement strategy for run-time measures to avoid potentially catastrophic consequences of timing dependencies which are not eliminated from the design. Their applicability is shown in experiments and case studies. However, all the proposed run-time measures as well as very strict implementation requirements become ever more expensive in terms of design effort for contemporary embedded systems, due to the system's complexity. Hence, the second part of this thesis reflects on the design aspect rather than the analysis aspect of embedded systems and proposes a timing predictable design paradigm based on System-Level Logical Execution Time (SL-LET). Leveraging a timing-design model in SL-LET the proposed methods from the first part can now be applied to improve the quality of a design -- timing error handling can now be separated from the run-time methods and from the implementation requirements intended to guarantee them. The thesis therefore introduces timing diversity as a timing-predictable execution theme that handles timing errors without having to deal with them in the implemented application. An automotive 3D-perception case study demonstrates the applicability of timing diversity to ensure predictable end-to-end timing while masking certain types of timing errors.Traditionell wurden Timing-Anforderungen als (technische) Sicherheitsanforderungen durch geschickte funktionale Entwürfe vermieden. Neue Fahrzeugautomatisierungskonzepte und Anwendungen machen dies jedoch schwieriger oder gar unmöglich; Aufgrund der Problemkomplexität erfordert dies eine Entwurfsautomatisierung für cyber-physische Systeme heraus. Diese Arbeit nimmt sich dieser Herausforderung an, indem sie eine schichtenübergreifende Abhängigkeitsanalyse einführt, um zeitliche Abhängigkeiten im Modell der beschränkten Ausführungszeit (BET) mit dem funktionalen Modell des Artefakts in Beziehung zu setzen. Auf diese Weise ist die Analyse in der Lage, aufzuzeigen, wo Timing-Abhängigkeiten die Anforderungen an die Störungsfreiheit auf der funktionalen Schicht und anderen dazwischenliegenden Modellschichten verletzen können. Für die Entwurfsautomatisierung ergibt sich daraus die Herausforderung, wie solche Abhängigkeiten vermieden oder zumindest so eingegrenzt werden können, dass der Entwurf machbar ist: Das Ergebnis sind Synthesestrategien für Implementierungsanforderungen und eine Platzierungsstrategie auf Systemebene für Laufzeitmaßnahmen zur Vermeidung potentiell katastrophaler Folgen von Timing-Abhängigkeiten, die nicht aus dem Entwurf eliminiert werden. Ihre Anwendbarkeit wird in Experimenten und Fallstudien gezeigt. Allerdings werden alle vorgeschlagenen Laufzeitmaßnahmen sowie sehr strenge Implementierungsanforderungen für moderne eingebettete Systeme aufgrund der Komplexität des Systems immer teurer im Entwurfsaufwand. Daher befasst sich der zweite Teil dieser Arbeit eher mit dem Entwurfsaspekt als mit dem Analyseaspekt von eingebetteten Systemen und schlägt ein Entwurfsparadigma für vorhersagbares Timing vor, das auf der System-Level Logical Execution Time (SL-LET) basiert. Basierend auf einem Timing-Entwurfsmodell in SL-LET können die vorgeschlagenen Methoden aus dem ersten Teil nun angewandt werden, um die Qualität eines Entwurfs zu verbessern -- die Behandlung von Timing-Fehlern kann nun von den Laufzeitmethoden und von den Implementierungsanforderungen, die diese garantieren sollen, getrennt werden. In dieser Arbeit wird daher Timing Diversity als ein Thema der Timing-Vorhersage in der Ausführung eingeführt, das Timing-Fehler behandelt, ohne dass sie in der implementierten Anwendung behandelt werden müssen. Anhand einer Fallstudie aus dem Automobilbereich (3D-Umfeldwahrnehmung) wird die Anwendbarkeit von Timing-Diversität demonstriert, um ein vorhersagbares Ende-zu-Ende-Timing zu gewährleisten und gleichzeitig in der Lage zu sein, bestimmte Arten von Timing-Fehlern zu maskieren

    Design of Time-Sensitive Networks For Safety-Critical Cyber-Physical Systems

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    A new era of Cyber-Physical Systems (CPSs) is emerging due to the vast growth in computation and communication technologies. A fault-tolerant and timely communication is the backbone of any CPS to interconnect the distributed controllers to the physical processes. Such reliability and timing requirements become more stringent in safety-critical applications, such as avionics and automotive. Future networks have to meet increasing bandwidth and coverage demands without compromising their reliability and timing. Ethernet technology is efficient in providing a low-cost scalable networking solution. However, the non-deterministic queuing delay and the packet collisions deny low latency communication in Ethernet. In this context, IEEE 802.1 Time Sensitive Network (TSN) standard has been introduced as an extension of the Ethernet technology to realize switched network architecture with real-time capabilities. TSN offers Time-Triggered (TT) traffic deterministic communication. Bounded Worst-Case end-to-end Delay (WCD) delivery is yielded by Audio Video Bridging (AVB) traffic. In this thesis, we are interested in the TSN design and verification. TSN design and verification are challenging tasks, especially for realistic safety-critical applications. The increasing complexity of CPSs widens the gap between the underlying networks' scale and the design techniques' capabilities. The existing TSN's scheduling techniques, which are limited to small and medium networks, are good examples of such a gap. On the other hand, the TSN has to handle dynamic traffic in some applications, e.g., Fog computing applications. Other challenges are related to satisfying the fault-tolerance constraints of mixed-criticality traffic in resource-efficient manners. Furthermore, in space and avionics applications, the harsh radiation environment implies verifying the TSN's availability under Single Event Upset (SEU)-induced failures. In other words, TSN design has to manage a large variety of constraints regarding the cost, redundancy, and delivery latency where no single design approach fits all applications. Therefore, TSN's efficient employment demands a flexible design framework that offers several design approaches to meet the broad range of timing, reliability, and cost constraints. This thesis aims to develop a TSN design framework that enables TSN deployment in a broad spectrum of CPSs. The framework introduces a set of methods to address the reliability, timing, and scalability aspects. Topology synthesis, traffic planning, and early-stage modeling and analysis are considered in this framework. The proposed methods work together to meet a large variety of constraints in CPSs. This thesis proposes a scalable heuristic-based method for topology synthesis and ILP formulations for reliability-aware AVB traffic routing to address the fault-tolerance transmission. A novel method for scalable scheduling of TT traffic to attain real-time transmission. To optimize the TSN for dynamic traffic, we propose a new priority assignment technique based on reinforcement learning. Regarding the TSN verification in harsh radiation environments, we introduce formal models to investigate the impact of the SEU-induced switches failures on the TSN availability. The proposed analysis adopts the model checking and statistical model checking techniques to discover and characterize the vulnerable design candidates

    Scheduling Rate Constrained traffic in End Systems of Time-Aware Networks

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    Nowadays, most of cyber-physical systems in avionics, automotive or recent Industry 4.0 domains require networked communication for mixed-critical applications. Ethernet-based networks such as AFDX, TTEthernet or TSN are capable to support transmission of both safety-critical and non-critical flows. This paper focuses on the TTEthernet network compliant with the avionics ARINC 664-P7 standard supporting time-triggered communication (TT) together with rate-constrained (RC) and best-effort (BE) traffic. Due to a global synchronization, TTcommunication with low latency and minimal jitter is ensured with static schedules computed offline. For event-triggered RC flows, bounded jitter at the source and end-to-end latency are guaranteed with worst-case analysis methods. With the increasing demands of applications, flows with Quality of Service (QoS) requirements such as video or audio may be transmitted as BE flows. However, on current configurations, no guarantees are offered to BE flows. In this paper, we aim at increasing the maximum RC utilization and improving the QoS of BE flows to allow the transmission of video or audio traffic with low jitter and end-to-end delay requirements. For this, we focus on the scheduling mechanisms and propose a scheduling approach based on a static slotted table that is applied at end systems. This table integrates the TT schedules usually obtained with Satisfiability Modulo Theories (SMT) approaches and establishes offsets of RC flows that reduce the end-to-end delay of BE flows. Several strategies for offset computations are proposed based on the distribution of flows locally at end system or globally at switch. We show that local strategies perform better than the global ones to reduce end-to-end delay of BE flows
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