Analog sinewave signal generators for mixed-signal built-in test applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.Gobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302Junta de Andalucía P09-TIC-538

A BIST solution for frequency domain characterization of analog circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder ÓÄ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

Guidelines for the efficient design of sinewave generators for analog/mixed-signal BIST

6 páginas, 12 figuras, 1 tabla.-- Congreso celenrado en La Grande Motte (Francia) del 7 al 9 de Junio del 2010.This paper presents a design methodology for the implementation of efficient and accurate sinewave generators suitable for analog and mixed-signal BIST applications. The design guidelines are based on an analytical discussion that contemplates the main non-idealities of the generator. A full design example is presented to illustrate the proposed methodology.This work has been funded in part by the Spanish Government through a JAE-DOC contract, and projects TEST (TEC2007-68072/MIC), SR2 (TSI-020400-2008-71/MEDEA + 2A105), TOETS (CATRENE CT302) and by the Junta de Andalucia through project ACATEX (P09-TIC-5386).Peer reviewe

Increasing Signal to Noise Ratio and Minimising Artefacts in Biomedical Instrumentation Systems

The research work described in this thesis was concerned with finding a novel method of minimising motion artefacts in biomedical instrumentation systems. The proposed solution, an Analog Frontend (AFE), was designed to detect any vertical (Y-Plane) or horizontal (X-Plane) movement of the electrode using two strain gauges, which were separated by 90° and fitted onto the electrode. The detected motion was fed back to the system for the removal of any motion artefact. The research started by emphasising the importance of minimising motion artefacts from biomedical signals and explaining how important it is for a clinical misinterpretation of the results. Hence, various motion artefact minimisation techniques undertaken by other researchers in the field were reviewed. This study covered different sources of artefacts, including the 40kHz powerline interference (PLI), 50/60kHz common-mode noise, white noise, and motion artefacts. The system was fully developed and tested and was firstly simulated using MATLAB Simulink tools to prove the effectiveness of the system before starting the implementation and build phase in the lab. The AFE system successfully produced a clean output signal, achieving an average correlation coefficient of 0.995. Also, the system output had a 98% SNR similarity with the clean source signal. Further, the system was then built and tested in the lab and successfully minimised the motion artefacts, achieving an average correlation coefficient of 0.974. Additionally, the final output had a 97.8% SNR similarity with the clean source signal. A novel test rig was developed to test the system with strain gauges. The system was able to remove the detected signal from the test rig and had an average correlation coefficient of 0.957. Lastly, the final output had a 94.2% SNR similarity with the clean source signal

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

A re-configurable pipeline ADC architecture with built-in self-test techniques

High-performance analog and mixed-signal integrated circuits are integral parts of today\u27s and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they\u27re operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs.;In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved.;A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications.;To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC\u27s 0.25mum single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-gain bandwidth. The experimental results strongly support the effectiveness of reconfiguration algorithm, which provides an average of 0.5bit ENOB improvement among the set of configurations. For many applications, this is a very significant performance improvement.;The BIST and re-configurability techniques proposed are not limited to pipeline ADCs only. The BIST methodology is applicable to many analog systems and the re-configurability is applicable to any analog pipeline system

Analog Reconfigurable Circuits

The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

From analog to digital

Analog-to-digital conversion and its reverse, digital-to-analog conversion, are ubiquitous in all modern electronics, from instrumentation and telecommunication equipment to computers and entertainment. We shall explore the consequences of converting signals between the analog and digital domains and give an overview of the internal architecture and operation of a number of converter types. The importance of analog input and clock signal integrity will be explained and methods to prevent or mitigate the effects of interference will be shown. Examples will be drawn from several manufacturers' datasheets