High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

One of the major challenges in high-speed input/output (HSIO) links electrical validation is the physical layer (PHY) tuning process. Equalization techniques are employed to cancel any undesired effect. Typical industrial practices require massive lab measurements, making the equalization process very time consuming. In this paper, we exploit the Broyden-based input space mapping (SM) algorithm to efficiently optimize the PHY tuning receiver (Rx) equalizer settings for a SATA Gen 3 channel topology. We use a good-enough surrogate model as the coarse model, and an industrial post-silicon validation physical platform as the fine model. A map between the coarse and the fine model Rx equalizer settings is implicitly built, yielding an accelerated SM-based optimization of the PHY tuning process

A Review of Bayesian Methods in Electronic Design Automation

The utilization of Bayesian methods has been widely acknowledged as a viable solution for tackling various challenges in electronic integrated circuit (IC) design under stochastic process variation, including circuit performance modeling, yield/failure rate estimation, and circuit optimization. As the post-Moore era brings about new technologies (such as silicon photonics and quantum circuits), many of the associated issues there are similar to those encountered in electronic IC design and can be addressed using Bayesian methods. Motivated by this observation, we present a comprehensive review of Bayesian methods in electronic design automation (EDA). By doing so, we hope to equip researchers and designers with the ability to apply Bayesian methods in solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which can be sent to [email protected]

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.ITESO, A.C

Advanced RF and Microwave Design Optimization: A Journey and a Vision of Future Trends

In this paper, we outline the historical evolution of RF and microwave design optimization and envisage imminent and future challenges that will be addressed by the next generation of optimization developments. Our journey starts in the 1960s, with the emergence of formal numerical optimization algorithms for circuit design. In our fast historical analysis, we emphasize the last two decades of documented microwave design optimization problems and solutions. From that retrospective, we identify a number of prominent scientific and engineering challenges: 1) the reliable and computationally efficient optimization of highly accurate system-level complex models subject to statistical uncertainty and varying operating or environmental conditions; 2) the computationally-efficient EM-driven multi-objective design optimization in high-dimensional design spaces including categorical, conditional, or combinatorial variables; and 3) the manufacturability assessment, statistical design, and yield optimization of high-frequency structures based on high-fidelity multi-physical representations. To address these major challenges, we venture into the development of sophisticated optimization approaches, exploiting confined and dimensionally reduced surrogate vehicles, automated feature-engineering-based optimization, and formal cognition-driven space mapping approaches, assisted by Bayesian and machine learning techniques.ITESO, A.C

An Early History of Optimization Technology for Automated Design of Microwave Circuits

This paper outlines the early history of optimization technology for the design of microwave circuits—a personal journey filled with aspirations, academic contributions, and commercial innovations. Microwave engineers have evolved from being consumers of mathematical optimization algorithms to originators of exciting concepts and technologies that have spread far beyond the boundaries of microwaves. From the early days of simple direct search algorithms based on heuristic methods through gradient-based electromagnetic optimization to space mapping technology we arrive at today’s surrogate methodologies. Our path finally connects to today’s multi-physics, system-level, and measurement-based optimization challenges exploiting confined and feature-based surrogates, cognition-driven space mapping, Bayesian approaches, and more. Our story recognizes visionaries such as William J. Getsinger of the 1960s and Robert Pucel of the 1980s, and highlights a seminal decades-long collaboration with mathematician Kaj Madsen. We address not only academic contributions that provide proof of concept, but also indicate early formative milestones in the development of commercially competitive software specifically featuring optimization technology.ITESO, A.C

System Margining Surrogate-Based Optimization in Post-Silicon Validation

There is an increasingly higher number of mixed-signal circuits within microprocessors. A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links is critical to provide a release qualification decision. One of the major challenges in HSIO electrical validation is the physical layer (PHY) tuning process, where equalization techniques are typically used to cancel any undesired effect. Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive lab measurements. On the other hand, surrogate modeling techniques allow to develop an approximation of a system response within a design space of interest. In this paper, we analyze several surrogate modeling methods and design of experiments techniques to identify the best approach to efficiently optimize a receiver equalizer. We evaluate the models performance by comparing with actual measured responses on a real server HSIO link. We then perform a surrogate-based optimization on the best model to obtain the optimal PHY tuning settings of a HSIO link. Our methodology is validated by measuring the real functional eye diagram of the physical system using the optimal surrogate model solution

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations