High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

Abstract

One of the major challenges in high-speed input/output (HSIO) links electrical validation is the physical layer (PHY) tuning process. Equalization techniques are employed to cancel any undesired effect. Typical industrial practices require massive lab measurements, making the equalization process very time consuming. In this paper, we exploit the Broyden-based input space mapping (SM) algorithm to efficiently optimize the PHY tuning receiver (Rx) equalizer settings for a SATA Gen 3 channel topology. We use a good-enough surrogate model as the coarse model, and an industrial post-silicon validation physical platform as the fine model. A map between the coarse and the fine model Rx equalizer settings is implicitly built, yielding an accelerated SM-based optimization of the PHY tuning process