Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current

The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-&kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-&kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing, DC biasing, and the design of current mirrors and differential amplifiers. They attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional (non-high-&kappa/metal gate) ultra-thin oxide CMOS technologies. They require only ultra-thin oxide devices and are investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. A sub-1 V bandgap voltage reference that requires only ultra-thin oxide MOSFETs is presented (TC = 251.0 ppm/°C). It utilizes the developed methodology and illustrates that it is capable of suppressing the negative effects of direct tunneling. Its performance is compared to a thick-oxide voltage reference as a means of demonstrating that ultra-thin oxide MOSFETs can be used to build the analog component of a mixed-signal system

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Photodetectors based on low-dimensional materials and hybrid systems

Premi extraordinari doctorat UPC curs 2015-2016, àmbit de CiènciesIn the last decade, two-dimensional (2D) materials have attracted attention both in the nascent field of flexible nanotechnology as well as in more conventional semiconductor technol-ogies. Within the rapidly expanding portfolio of 2D materials, the group of semiconducting transition metal dichalcogenides (TMDCs) has emerged as an intriguing candidate for various optoelectronic applications. The atomically thin profile, favorable bandgap and outstanding electronic properties of TMDCs are unique features that can be explored and applied in novel photodetecting platforms. This thesis presents highly sensitive two-dimensional phototransistors made of sub-nanometre thick TMDC channels. Firstly, an encapsulation route is developed to address the detrimental and, to date, uncontrollable impact of atmospheric adsorbates, which severely deteriorate detector performance. The passivation scheme improves the transport properties of TMDCs, leading to high photoconductive gain with gate dependent responsivity of 10 -10^4 A/W throughout the visible, and temporal response down to 10 ms, which is suitable for imaging applications. The atomic device thickness yields ultra-low dark current operation and record detectivity of 10^11 - 10^12 Jones for TMDC-based detectors is achieved. The use of monolayer TMDCs, however, has disadvantages like limited spectral absorption due to the bandgap and limited absorption efficiency. In order to increase the absorption and to extend the spectral coverage, TMDC channels are covered with colloidal quantum dots to make hybrid phototransistors. This compelling synergy combines strong and size-tunable light absorption within the QD film, efficient charge separation at the TMDC-QD interface and fast carrier transport through the 2D channel. This results in large gain of 10^6 electrons per absorbed photon and creates the basis for extremely sensitive light sensing. Colloidal quan-tum dots are an ideal sensitizer, because their solution-processing and facile implementation on arbitrary substrates allows for low-cost fabrication of hybrid TMDC-QD devices. Moreover, the custom tailored bandgap of quantum dots provides the photodetector with wide spectral tunability. For photodetection in the spectral window of NIR/SWIR, which is still dominated by expensive and complex epitaxy-based technologies, these hybrid detectors have the potential to favorably compete with commercially available systems. The interface of the TMDC-QD hybrid is of paramount importance for sensitive detector operation. A high density of trap states at the interface is shown to be responsible for inefficient gate-control over channel conductivity, which leads to high dark currents. To maintain the unique electrical field-effect modulation in TMDCs upon deposition of colloidal quantum dots, a passivation route of the interface with semiconducting metal-oxide films is developed. The buffer-layer material is selected such that charge transfer from QDs into the channel is favored. The retained field-effect modulation with a large on/off ratio allows operation of the phototransistor at significantly lower dark currents than non-passivated hybrids. A TMDC-QD phototransistor with an engineered interface that exhibits detectivity of 10^12 - 10^13 Jones and response times of 12 ms and less is reported. In summary, this work showcases prototype photodetectors made of encapsulated 2D TMDCs and TMDC-QD hybrids. Plain TMDC-detectors have potential for application as flexible and semi-transparent detector platforms with high sensitivity in the visible. The hybrid TMDC-QD device increases its spectral selectivity to the NIR/SWIR due to the variable absorption of the sensitizing quantum dots and reaches compelling performance thanks to im-proved light-matter interaction and optimized photocarrier generation.En la última década ha surgido un gran interés por los materiales bidimensionales (2D) tanto para las tecnologías emergentes de dispositivos flexibles, como para las tecnologías de semiconductores tradicionales. Dentro del creciente catálogo de materiales 2D, los semiconductores basados en dicalcogenuros de metales de transición (DCMTs) han surgido como candidatos para aplicaciones optoelectrónicas. Sus características únicas, tales como grosor atómico, banda prohibida y propiedades electrónicas pueden ser examinadas y aplicadas en nuevas plataformas de fotodetección. En esta tesis se presentan nuevos fototransistores bidimensionales ultrasensibles basados en canales de DCMTs subnanométricos. Se presenta una ruta de encapsulación para intentar solucionar el impacto negativo, e incontrolable hasta la fecha, producido por la adsorción de sustancias atmosféricas que degradan el funcionamiento de los detectores. Este proceso mejora el transporte en los DCMTs dando lugar a una gran ganancia fotoconductora, una respuesta, dependiente de la tensión aplicada en el gate, de 10-10^4 A/W en el visible y una respuesta temporal de tan solo 10 ms, todo ello adecuado para aplicaciones de imagen. El grosor atómico de los dispositivos da lugar a corrientes de oscuridad muy bajas y una detectividad de 10^11-10^12 Jones. Sin embargo, el uso de monocapas de DCMTs presenta ciertas desventajas como por ejem-plo una eficiencia en la absorción baja. Con el fin de mejorar la absorción, los canales de DCMTs se han recubierto con puntos cuánticos (QDs) para fabricar fototransistores híbridos. Esta sinergia combina la alta absorción de los QDs, una eficiente separación de cargas en la interfaz DCMT-QD y un rápido transporte de cargas a través del canal 2D. Todo esto resulta en una ganancia de 10^6 electrones por fotón absorbido y crea la base para sensores de luz extremadamente sensibles. Los puntos cuánticos coloidales son sensibizadores ideales ya que su procesado en disolución y su fácil incorporación sobre cualquier sustrato permiten la fabricación de sistemas híbridos DCMT-QD a bajo coste. Además, la posibilidad de modifi-car la banda prohibida, ofrecida por los QDs, proporciona al fotodetector una amplia respuesta espectral. Para fotodetección en la ventana espectral del infrarrojo cercano (NIR/SWIR), estos detectores híbridos presentan el potencial de competir favorablemente con los sistemas comerciales disponibles. La interfaz entre el híbrido DCMT-QD es de la mayor importancia para la sensibilidad del detector. Se ha demostrado que una alta densidad de trampas en la interfaz es la responsable del ineficiente control mediante el gate de la conductividad del canal, dando lugar a corrientes de oscuridad muy altas. Para mantener la excepcional modulación de efecto campo aún después de la deposición de los QDs, se ha desarrollado una ruta de pasivación de la interfaz con óxidos metálicos semiconductores. El material de esta capa amortiguadora (buffer) es seleccionado de tal manera que permita la transferencia de cargas desde los puntos cuánticos hasta el canal DCMT. Esto retiene la modulación de efecto campo con una relación encendido/apagado muy alta, permitiendo el funcionamiento del fototransistor con corrientes de oscuridad significativamente menores que las de los híbridos sin pasivar. Así, se presenta un fototransistor híbrido DCMT-QD, con una interfaz cuidadosamente diseñada, que exhibe una detectividad de 10^12-10^13 Jones. En resumen, este trabajo presenta unos prototipos de fotodetectores basados en DCMT 2D encapsulados y en híbridos DCMT-QD. Los fotodetectores basados en DCMT simples presentan potencial para su aplicación en detectores flexibles y semitransparentes, con gran sensibilidad en el visible. Los híbridos DCMT-QD amplían la selectividad espectral al infrarrojo cercano gracias a la absorción variable ofrecida por los puntos cuánticos y alcanzan un muy interesante rendimiento gracias a una mejor interacción luz-materia.Award-winningPostprint (published version

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration