Algorithmic studies on PCB routing

As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a pin count of thousands. As a result, a complex printed circuit board (PCB) can host more than ten thousand signal nets. Such a huge pin count and net count make manual design of packages and PCBs an extremely time-consuming and error-prone task. On the other hand, increasing clock frequency imposes various physical constraints on PCB routing. These constraints make traditional IC and PCB routers not applicable to modern PCB routing. To the best of our knowledge, there is no mature commercial or academic automated router that handles these constraints well. Therefore, automated PCB routers that are tuned to handle such constraints become a necessity in modern design. In this dissertation, we propose novel algorithms for three major aspects of PCB routing: escape routing, area routing and layer assignment. Escape routing for packages and PCBs has been studied extensively in the past. Network flow is pervasively used to model this problem. However, previous studies are incomplete in two senses. First, none of the previous works correctly model the diagonal capacity, which is essential for 45 degree routing in most packages and PCBs. As a result, existing algorithms may either produce routing solutions that violate the diagonal capacity or fail to output a legal routing even though one exists. Second, few works discuss the escape routing problem of differential pairs. In high-performance PCBs, many critical nets use differential pairs to transmit signals. How to escape differential pairs from a pin array is an important issue that has received too little attention in the literature. In this dissertation, we propose a new network flow model that guarantees the correctness when diagonal capacity is taken into consideration. This model leads to the first optimal algorithm for escape routing. We also extend our model to handle missing pins. We then propose two algorithms for the differential pair escape routing problem. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. In our routing scheme, the second algorithm is used to generate initial routing and the first algorithm is used to perform rip-up and reroute. Length-constrained routing is another very important problem for PCB routing. Previous length-constrained routers all have assumptions on the routing topology. We propose a routing scheme that is free of any restriction on the routing topology. The novelty of our proposed routing scheme is that we view the length-constrained routing problem as an area assignment problem and use a placement structure to help transform the area assignment problem into a mathematical programming problem. Experimental results show that our routing scheme can handle practical designs that previous routers cannot handle. For designs that they could handle, our router runs much faster. Length-constrained routing requires the escaped nets to have matching ordering along the boundaries of the pin arrays. However, in some practical designs, the net ordering might be mismatched. To address this issue, we propose a preprocessing step to untangle such twisted nets. We also introduce a practical routing style, which we call single-detour routing, to simplify the untangling problem. We discover a necessary and sufficient condition for the existence of single-detour routing solutions and present a dynamic programming based algorithm that optimally solves the problem. By integrating our algorithm into the bus router in a length-constrained router, we show that many routing problems that cannot be solved previously can now be solved with insignificant increase in runtime. The nets on a PCB are usually grouped into buses. Because of the high pin density of the packages, the buses need to be assigned into multiple routing layers. We propose a layer assignment algorithm to assign a set of buses into multiple layers without causing any conflict. Our algorithm guarantees to produce a layer assignment with minimum number of layers. The key idea is to transform the layer assignment problem into a bipartite matching problem. This research result is an improvement over a previous work, which is optimal for only one layer

Layer assignment and routing optimization for advanced technologies

As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to achieve timing closure for VLSI design. Since a complete design flow consists of several phases, such as logic synthesis, placement, and routing, interconnect synthesis plays an important role which includes buffer insertion/sizing and timing-driven routing. Although progress has been achieved by many advanced routing techniques, the following aspects can be exploited sufficiently for further improvement: (1) incremental layer assignment for timing optimization; (2) signal routing with the requirement of regularity; (3) power-efficient optical-electrical interconnect paradigm. Thus, to perform the layer assignment and routing optimization for advanced technologies, an automated routing engine in a global view is essential to benefit the interconnect design while satisfying specific requirements. This dissertation proposes a set of algorithms and methodology on layer assignment and routing optimization for advanced technologies. The research includes two timing-driven incremental layer assignment approaches, synergistic topology generation and routing synthesis for signal groups, and optical-electrical routing design for power efficiency. For incremental layer assignment, most of the conventional approaches target via minimization but neglect the timing issues. Meanwhile, via delays are ignored but should be considered in emerging technology nodes. Then two timing-driven incremental layer assignment frameworks are proposed, where all the nets are solved simultaneously with the integration of via delays: (1) optimization of the total sum of net delays and reduction of slew violations; (2) minimization of critical path timing in selected nets. For on-chip signal routing, the bundled bits in one group may have different pin locations, but they have to be routed in a regular manner by sharing common topologies. Very few previous works target inter-bit regularity via multi-layer topology selection. Furthermore, the routability and wire-length of the signal bits should also be optimized. Then an advanced synergistic routing engine is promoted, which is able to not only control routability and wire-length but also guide each bit routing intelligently for design regularity. For optical-electrical co-design routing, optical interconnect shows its advantage due to the dominance of bandwidth-distance-power properties. The previous works lack a detailed exploration of optical-electrical co-design for on-chip interconnects. During the transmission, signal quality can be affected by various loss sources and Electrical to Optical (EO)/Optical to Electrical (OE) conversion overheads should also be considered. Then a power-efficient routing flow for on-chip signals is presented, where optical connections can collaborate with electrical wires seamlessly. The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches are able to achieve the improvements regarding specific metrics and eventually benefit the routing flow.Electrical and Computer Engineerin

Researching methods for efficient hardware specification, design and implementation of a next generation communication architecture

The objective of this work is to create and implement a System Area Network (SAN) architecture called EXTOLL embedded in the current world of systems, software and standards based on the experiences obtained during the ATOLL project development and test. The topics of this work also cover system design methodology and educational issues in order to provide appropriate human resources and work premises. The scope of this work in the EXTOLL SAN project was: • the Xbar architecture and routing (multi-layer routing, virtual channels and their arbitration, routing formats, dead lock aviodance, debug features, automation of reuse) • the on-chip module communication architecture and parts of the host communication • the network processor architecture and integration • the development of the design methodology and the creation of the design flow • the team education and work structure. In order to successfully leverage student know-how and work flow methodology for this research project the SEED curricula changes has been governed by the Hochschul Didaktik Zentrum resulting in a certificate for "Hochschuldidaktik" and excellence in university education. The complexity of the target system required new approaches in concurrent Hardware/Software codesign. The concept of virtual hardware prototypes has been established and excessively used during design space exploration and software interface design

Design and Implementation of the Precision Personnel Locator Digital Transmitter System

The Precision Personnel Locator project is an ongoing research project funded by the Department of Justice, the goal of which is to provide sub-meter accuracy tracking and location of first responders inside of buildings with no pre-existing infrastructure, especially in emergency situations. The PPL system consists of wearable, battery-powered Locator devices that transmit a multi-carrier “ranging signal†waveform and Reference Units that receive this ranging signal and relay the information to a Base Station for location estimation processing and display. This thesis describes the design and implementation of a subset of the Locator devices’ functionality, including: the digital generation of the ranging signal waveform; the coordination of the transmissions of many Locator devices using time-sharing methods to prevent overlap of the signals; and finally, the gathering of environmental data such as temperature and movement of the wearer and the relaying of this data back to the Base Station. To perform these tasks, two subsystems were designed and implemented as printed circuit boards. The first of these is the Data Channel, which is a low power, general-purpose communications platform that is capable of controlling the transmissions of the Locator devices with support for up to 100 Locators transmitting every second, and it can control the power of the Locator devices by switching portions of the system off when they are not in use. It also includes sensors to measure the ambient temperature, movement of the device, and a “distress button†that a first responder can press to trigger a distress signal to be transmitted to the outside of the building. The second subsystem is the Digital Waveform Generator, which consists of a Field-Programmable Gate Array (FPGA) and Digital-to-Analog Converter (DAC) that are capable of generating waveforms of up to 200 MHz bandwidth. The new Locator hardware can operate on battery power for many days. The two subsystems were successfully tested and will serve as an important step towards the goal of developing a deployable location and tracking system

AI Knowledge Transfer from the University to Society

AI Knowledge Transfer from the University to Society: Applications in High-Impact Sectors brings together examples from the "Innovative Ecosystem with Artificial Intelligence for Andalusia 2025" project at the University of Seville, a series of sub-projects composed of research groups and different institutions or companies that explore the use of Artificial Intelligence in a variety of high-impact sectors to lead innovation and assist in decision-making. Key Features Includes chapters on health and social welfare, transportation, digital economy, energy efficiency and sustainability, agro-industry, and tourism Great diversity of authors, expert in varied sectors, belonging to powerful research groups from the University of Seville with proven experience in the transfer of knowledge to the productive sector and agents attached to the Andalucía TECH Campu

Modeling of vias and via arrays in high speed printed circuit boards

This thesis presents modeling approaches for fast calculation of signals in dense via arrays in high speed printed circuit boards (PCBs) and model to hardware correlation study of solid and perforated disk resonators. A 2D finite difference (FD) method to extract the via capacitance which includes the via pad capacitance obtained by solving the laplace equation in the via domain in multi-layer geometries is presented and validated with analytical formulation for via capacitance. Next, closed-form expression for the impedance of an infinitely large parallel plane pair is derived and validated by comparing with cavity model for several numerical examples. The infinitely large parallel plane pair model is applicable to practical printed circuit board (PCB) design problems where there are multiple shorting vias around the signal vias of interest. With the presence of multiple shorting vias, reflections from the plane pair edges can be neglected since the shorting vias prevent the electromagnetic energy from leaking away from the local cavity around the signal vias. Next, improved multiple scattering method for fast calculation of signals in via arrays in plane pair is derived using analytical expressions. Parallel plate modes expressed as cylindrical waves are excited by the magnetic frill currents in via holes (antipads). Multiple scattering of these modes among vias as well as from the edge boundaries of the plate pair are rigorously considered with the addition theorem of the cylindrical waves. In the final part of this thesis, different approaches mentioned here are applied to study solid and perforated disk resonator behaviors and to correlate the simulated and measured results --Abstract, page iii

Super Ball Bot - Structures for Planetary Landing and Exploration, NIAC Phase 2 Final Report

Small, light-weight and low-cost missions will become increasingly important to NASA's exploration goals. Ideally teams of small, collapsible, light weight robots, will be conveniently packed during launch and would reliably separate and unpack at their destination. Such robots will allow rapid, reliable in-situ exploration of hazardous destination such as Titan, where imprecise terrain knowledge and unstable precipitation cycles make single-robot exploration problematic. Unfortunately landing lightweight conventional robots is difficult with current technology. Current robot designs are delicate, requiring a complex combination of devices such as parachutes, retrorockets and impact balloons to minimize impact forces and to place a robot in a proper orientation. Instead we are developing a radically different robot based on a "tensegrity" structure and built purely with tensile and compression elements. Such robots can be both a landing and a mobility platform allowing for dramatically simpler mission profile and reduced costs. These multi-purpose robots can be light-weight, compactly stored and deployed, absorb strong impacts, are redundant against single-point failures, can recover from different landing orientations and can provide surface mobility. These properties allow for unique mission profiles that can be carried out with low cost and high reliability and which minimizes the inefficient dependance on "use once and discard" mass associated with traditional landing systems. We believe tensegrity robot technology can play a critical role in future planetary exploration

AI Knowledge Transfer from the University to Society

AI Knowledge Transfer from the University to Society: Applications in High-Impact Sectors brings together examples from the "Innovative Ecosystem with Artificial Intelligence for Andalusia 2025" project at the University of Seville, a series of sub-projects composed of research groups and different institutions or companies that explore the use of Artificial Intelligence in a variety of high-impact sectors to lead innovation and assist in decision-making. Key Features Includes chapters on health and social welfare, transportation, digital economy, energy efficiency and sustainability, agro-industry, and tourism Great diversity of authors, expert in varied sectors, belonging to powerful research groups from the University of Seville with proven experience in the transfer of knowledge to the productive sector and agents attached to the Andalucía TECH Campu

Hypergraph-Based Interconnection Networks for Large Multicomputers

This thesis deals with issues pertaining to multicomputer interconnection networks namely topology, technology, switching method, and routing algorithm. It argues that a new class of regular low-dimensional hypergraph networks, the distributed crossbar switch hypermesh (DCSH), represents a promising alternative high-performance interconnection network for future large multicomputers to graph networks such as meshes, tori, and binary n-cubes, which have been widely used in current multicomputers. Channels in existing hypergraph and graph structures suffer from bandwidth limitations imposed by implementation technology. The first part of the thesis shows how the low-dimensional DCSH can use an innovative implementation scheme to alleviate this problem. It relies on the separation of processing and communication functions by physical layering in order to accommodate high wiring density and necessary message buffering, improving performance considerably. Various mathematical models of the DCSH, validated through discrete-event simulation, are then introduced. Effects of different switching methods (e.g., wormhole routing, virtual cut-through, and message switching), routing algorithms (e.g., restricted and random), and different switching element designs are investigated. Further, the impact on performance of different communication patterns, such as those including locality and hot-spots, are assessed. The remainder of the thesis compares the DCSH to other common hypergraph and graph networks assuming different implementation technologies, such as VLSI, multiple-chip technology, and the new layered implementation scheme. More realistic assumptions are introduced such as pipeline-bit transmission and non-zero delays through switching elements. The results show that the proposed structure has superior characteristics assuming equal implementation cost in both VLSI and multiple-chip technology. Furthermore, optimal performance is offered by the new layered implementation