A Study of Ozone as an Oxygen Source for the Growth of High-Κ Dielectric Films for Gate Dielectric on GaN/AlGaN/GaN

GaN is a promising alternative to silicon technology for the next-generation high-power and high-frequency electronics. The choice stems from the intrinsic properties of GaN of a wide bandgap and consequently high breakdown voltage, high saturation electron velocity and good thermal conductivity. Spontaneous and piezoelectric polarization effects cause accumulation of a high density of carriers at III-Nitride heterointerfaces enabling engineering of high mobility channels. The primary factor inhibiting the further growth of GaN HEMTs is the high leakage current leading to device unreliability. The MIS-structure used in Si-CMOS processing has been adapted and shown to reduce leakage current in GaN technology. However, the introduction of an insulator adds another interface which suffers from poor quality due to innumerable traps with varying time constants. This leads to device threshold voltage instability and drain current collapse, while decreasing the device transconductance due to the increased gate-to-channel spatial separation. High-K dielectrics have been shown to reduce leakage current with smaller decrease in transconductance in Si-CMOS technology and therefore, applied to GaN technology. ALD is recognized as a novel method for high-κ gate dielectric deposition, where H2O is primarily used as the oxygen source for growth; excellent properties have been reported. However, ozone-grown films show further suppressed leakage current and offer better interfacial quality on silicon. In this study, MOSCaps have been developed on GaN/AlGaN/GaN heterostructures with PECVD Si3N4 and ALD HfO2 as the passivation layer and gate dielectric, respectively. HfO2 was grown using either H2O or ozone as the oxygen source. XPS analysis, capacitance-voltage, conductance-voltage and leakage current-voltage characteristics have been used as probes to study the quality of the film and its interface with the III-N semiconductor. It is observed that due to the sufficient supply of oxygen, ozone helps in the formation of a better bulk dielectric by more complete oxidation. However, the interface is degraded by uncontrolled surface oxidation of the barrier layer or/and penetration of oxygen impurities, creating shallow donor traps aiding in leakage. The overall leakage current with the ozone-grown dielectric is reduced by almost half-an-order of magnitude due to the better bulk dielectric achieved

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Characterization of Electrically Active Defects in Advanced Gate Dielectrics

As the gate oxide thickness of the metal-oxide-semiconductor (MOS) Field Effect Transistor (FET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding device reliability. Substitute dielectrics with high dielectric constant (high-k) have been proposed to replace traditional SiO2 to reduce the leakage current in future devices. However, these high-k dielectrics also have reliability issues due to the large amount of intrinsic trapping centers. In this work, electrically active defects generated during electrical stress of ultrathin SiO2 dielectrics are characterized and studied. The mechanism of oxide breakdown is studied by investigating the contributions of hot holes to device time-to-breakdown (tbd). The proper extrapolation of tbd from accelerated testing conditions to normal device operating conditions is also studied. The factors that affect this extrapolation are discussed. Another important device reliability parameter, threshold voltage shift (Vth), is also investigated in this work. The dominant mechanisms causing this shift is studied using both simulation and experimental results. The current primary reliability issue with high-k dielectrics is the large amount of intrinsic traps located in the dielectric stack. Therefore, the electrical characterization of high-k dielectrics in this work is focused on these initial as-fabricated trapping centers. A methodology based on 2-level charge pumping (CP) measurements at different frequencies is used to study the spatial profile of these trapping centers. The correlation between device fabrication data and measurement results indicates this methodology is accurate and reliable

Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Ion implantation is a nonequilibrium doping technique, which introduces impurity atoms into a solid regardless of thermodynamic considerations. The formation of metastable alloys above the solubility limit, minimized contribution of lateral diffusion processes in device fabrication, and possibility to reach high concentrations of doping impurities can be considered as distinct advantages of ion implantation. Due to excellent controllability, uniformity, and the dose insensitive relative accuracy ion implantation has grown to be the principal doping technology used in the manufacturing of integrated circuits. Originally developed from particle accelerator technology, ion implanters operate in the energy range from tens eV to several MeV (corresponding to a few nms to several microns in depth range). Ion implantation introduces point defects in solids. Very minute concentrations of defects and impurities in semiconductors drastically alter their electrical and optical properties. This chapter presents methods of defect spectroscopy to study the defect origin and characterize the defect density of states in thin film and semiconductor interfaces. The methods considered are positron annihilation spectroscopy, electron spin resonance, and approaches for electrical characterization of semiconductor devices

High Quality Gate Dielectric/MoS2 Interfaces Probed by the Conductance Method

Two-dimensional materials provide a versatile platform for various electronic and optoelectronic devices, due to their uniform thickness and pristine surfaces. We probe the superior quality of 2D/2D and 2D/3D interfaces by fabricating molybdenum disulfide (MoS2)-based field effect transistors having hexagonal boron nitride (h-BN) and Al2O3 as the top gate dielectrics. An extremely low trap density of ~7x10^10 states/cm2-eV is extracted at the 2D/2D interfaces with h-BN as the top gate dielectric on the MoS2 channel. 2D/3D interfaces with Al2O3 as the top gate dielectric and SiOx as the nucleation layer exhibit trap densities between 7x10^10 and 10^11 states/cm2-eV, which is lower than previously reported 2D-channel/high-k-dielectric interface trap densities. The comparable values of trap time constants for both interfaces imply that similar types of defects contribute to the interface traps. This work establishes the case for van der Waals systems where the superior quality of 2D/2D and 2D/high-k dielectric interfaces can produce high performance electronic and optoelectronic devices

Dielectrics for Two-Dimensional Transition Metal Dichalcogenide Applications

Despite over a decade of intense research efforts, the full potential of two-dimensional transition metal dichalcogenides continues to be limited by major challenges. The lack of compatible and scalable dielectric materials and integration techniques restrict device performances and their commercial applications Conventional dielectric integration techniques for bulk semiconductors are difficult to adapt for atomically thin two-dimensional materials. This review provides a brief introduction into various common and emerging dielectric synthesis and integration techniques and discusses their applicability for 2D transition metal dichalcogenides. Dielectric integration for various applications is reviewed in subsequent sections including nanoelectronics, optoelectronics, flexible electronics, valleytronics, biosensing, quantum information processing, and quantum sensing. For each application, we introduce basic device working principles, discuss the specific dielectric requirements, review current progress, present key challenges, and offer insights into future prospects and opportunities

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

Journal of Telecommunications and Information Technology, 2007, nr 2

kwartalni

Characterisation of charge carrier defects in high-dielectric-metal-gate and thin film transistor devices

Metal oxide semiconductor (MOS) transistors find application either as a switch or amplifier in high and low power electronic devices. In both sectors, devices rely on the availability of a good insulator layer for achieving desirable performance. The traditional CMOS transistors with Silicon (Si) semiconductor and SiO2 gate insulator has reached its limits with regards to supporting the need for faster and smaller devices. In low power CMOS technology high-dielectric (high-k) materials are being used to replace SiO2 insulator to minimise gate leakage current that arises as a result of device scaling. Another emerging field of application of electronic devices is the field of flat panel displays that aims to make use of transparent thin film MOS transistors. Alternate materials to amorphous silicon (a-Si:H) and poly-silicon (poly-Si) are being researched, to fabricate thin film transistors (TFTs), in favour of traditional materials that have limited optical transparency and mobility. Again, these TFTs are surely in need of good insulators to achieve stable operation against threshold voltage shifts. Performance of MOS transistors is highly dependent on the density of defects in the device. Defects in a transistor could be due to the inherent charge traps in the device materials or the traps formed during fabrication. These charge traps can affect the performance of a transistor such as causing shift in threshold voltage and degrading device mobility and also affect the reliability and stability of the device. Hence it becomes necessary to determine the cause, quantity and impact of defects so that better materials and/or better fabrication processes could be devised to obtain efficient devices. In this work the aim is to investigate the different defects/traps that impact MOS transistors employed in CMOS and transparent TFT technologies and also to study the impact of these defects on device mobility. Electrical current and capacitance measurements are carried out along with analytical modelling to quantify and understand the nature of the defects in the devices. Charge trap generation and distribution due to post-metallisation annealing of HfO2 based MOS transistor is studied. The density of defects in a ZnO based TFT with Ta2O5 gate insulator is also investigated in this study