A -5 dBm 400MHz OOK Transmitter for Wireless Medical Application

A 400 MHz high efficiency transmitter forwireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies isproposed to achieve high data rate with low powerconsumption. In the on-off keying transmitters, the oscillatorand power amplifier are turned off when the transmittersends 0 data. The proposed class-e power amplifier has highefficiency for low level output power. The proposed on-offkeying transmitter consumes 1.52 mw at -5 dBm output by 40Mbps data rate and energy consumption 38 pJ/bit. Theproposed transmitter has been designed in 0.18µm CMOStechnology

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

Ph.DDOCTOR OF PHILOSOPH

Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

Millimeter-scale RF Integrated Circuits and Antennas for Energy-efficient Wireless Sensor Nodes

Recently there has been increased demand for a millimeter-scale wireless sensor node for applications such as biomedical devices, defense, and surveillance. This form-factor is driven by a desire to be vanishingly small, injectable through a needle, or implantable through a minimally-invasive surgical procedure. Wireless communication is a necessity, but there are several challenges at the millimeter-scale wireless sensor node. One of the main challenges is external components like crystal reference and antenna become the bottleneck of realizing the mm-scale wireless sensor node device. A second challenge is power consumption of the electronics. At mm-scale, the micro-battery has limited capacity and small peak current. Moreover, the RF front-end circuits that operates at the highest frequency in the system will consume most of the power from the battery. Finally, as node volume reduces, there is a challenge of integrating the entire system together, in particular for the RF performance, because all components, including the battery and ICs, need to be placed in close proximity of the antenna. This research explores ways to implement low-power integrated circuits in an energy-constrained and volume constrained application. Three different prototypes are mainly conducted in the proposal. The first is a fully-encapsulated, autonomous, complete wireless sensor node with UWB transmitter in 10.6mm3 volume. It is the first time to demonstrate a full and stand-alone wireless sensing functionality with such a tiny integrated system. The second prototype is a low power GPS front-end receiver that supports burst-mode. A double super-heterodyne topology enables the reception of the three public GPS bands, L1, L2 and L5 simultaneously. The third prototype is an integrated rectangular slot loop antenna in a standard 0.13-μm BiCMOS technology. The antenna is efficiently designed to cover the bandwidth at 60 GHz band and easily satisfy the metal density rules and can be integrated with other circuitry in a standard process.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/143972/1/hskims_1.pd

Amplificador de potência CMOS de baixo consumo com controle de ganho

Orientador : Prof. André A. Mariano, Ph.D.Co-orientador : Prof. Bernardo Leite, Ph.D.Dissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa: Curitiba, 27/03/2015Inclui referênciasÁrea de concentração: Sistemas EletrônicosResumo: Devido ao baixo custo e alto grau de integração das tecnologias CMOS, os sistemas de comunicações móveis podem ser encontrados em toda parte. Em sua grande maioria, os dispositivos móveis são alimentados por baterias, sendo indispensável recarregá-las ou substituí-las. Nesta situação, deve-se tomar cuidados para que os dispositivos sejam energeticamente eficientes. Em um transmissor de radiofrequência, o amplificador de potência é o bloco responsável por amplificar o sinal que será transmitido pela antena. Por sua vez, o amplificador de potência é um dos responsáveis pelo maior consumo de energia do sistema. Como estes amplificadores são tradicionalmente dimensionados para apresentar alto rendimento para níveis elevados de potência de saída, em níveis mais baixos de potência de saída a energia consumida é excessiva. Portanto, controlar o ganho e a potência de saída em amplificadores de potência de radiofrequência é essencial para maximizar a duração da vida útil da bateria. Neste trabalho, um amplificador de potência com controle de ganho é apresentado para aplicações em 2,4 GHz. O ganho de potência pode ser controlado digitalmente em seis modos através da combinação de três bits. Esta técnica foi utilizada para alcançar uma melhora na eficiência em potências de recuo. O projeto foi implementado usando uma tecnologia CMOS 0,13 ?m e é capaz de fornecer um ganho de potência variável entre 22,4 dB e 31 dB e uma eficiência máxima de 19 %, com uma fonte de alimentação de 1,8 V. A potência consumida pelo amplificador é reduzida de 196,2 mW no modo de maior ganho para 171 mW no modo de menor ganho, permitindo uma eficiência melhor quando o ganho máximo não é necessário para a transmissão. Palavras-chave: amplificador de potência; ganho variável; controle discreto de potência; CMOS; radiofrequênciaAbstract: Due to the low cost and high degree of integration of CMOS technologies, mobile communication systems can be found everywhere. Most of these mobile devices are powered by batteries, which must be recharged or replaced. In this situation, care must be taken for the devices to be energetically efficient. In a radiofrequency transmitter, the power amplifier is responsible for amplifying the signal to be transmitted by the antenna and accounts for a large part of the system power consumption. Since these amplifiers are traditionally sized to present their highest efficiency for high output power levels, when the required output power is lower, energy consumption is excessive. Therefore, controlling the gain and output power in radiofrequency power amplifiers is essential to maximize the duration of battery life. In this work, a power amplifier with gain control is presented for 2.4 GHz applications. The power gain can be digitally controlled in six steps by the combination of three bits. This technique was used to achieve an improvement in efficiency at power backoff. The design was implemented using a 0.13 ?m CMOS technology and is able to deliver a variable power gain between 22.4 dB and 31 dB and a peak power-added efficiency of 19 % with a 1.8 V power supply. The power consumption of the power amplifier is reduced from 196.2 mW in the highest-gain mode to 171 mW for the lowest-gain, allowing an enhanced efficiency when maximum gain is not required for transmission. Keywords: power amplifier; variable gain; discrete power control; CMOS; radiofrequenc

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz