Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

This paper proposes the novel low power and area efficient ALU (Arithmetic and Logic Unit) using adder and multiplexers. The adder and multiplexer are realized by using CNTFET (Carbon Nano Tube Field Effect Transistor) A verilog model of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in cadence spice software. The proposed ALU is simulated using Monte carlo simulation at 0.9 sub threshold voltage tested with 45 nm technology for the measurement of power and transistor counts. The power consumption of CNTFET based ALU is found to be 45.67 % better than the existing technologies

NOVEL SINGLE LAYER FAULT TOLERANCE RCA CONSTRUCTION FOR QCA TECHNOLOGY

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCADesigner tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time

Current-Voltage characteristics of carbon Nanotube field effect transistor considering Non-Ballistic conduction

This thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2013.Cataloged from PDF version of thesis report.Includes bibliographical references (page 103-112).The need for technological advancement in the field of electronics has been ever increasing. Till now silicon has been the prime material of choice for meeting the current demands. However, silicon has its own limitations; Silicon based integrated circuits and the scaling of silicon MOSFET design faces complications like tunneling effect, gate oxide thickness effect etc. which has given the scope for new materials to emerge. The growing academic interest in carbon nanotubes (CNT) as a promising novel class of electronic material has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. In a nanotube, low bias transport can be nearly ballistic across distances of several hundred nanometers. Non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomenon, including elastic, phonon scattering, strain and tunneling effects, have been developed. The purpose of this paper is to establish a comparative analysis of the transport characteristics of ballistic and non-ballistic carbon nanotubes. The simulation is carried out using MATLAB and the main focus is on the changes in the I-V characteristic curves of elastic scattering effect, bandgap strain effect, tunneling effect and the overall combined effect, varying the parameters such as gate oxide thickness, temperature, dielectric constant, and chirality. The obtained results were then compared to their respective ballistic results. We verified our work by further comparison of our findings with other established academic papers published under the same category.Nirjhor Tahmidur RoufAshfaqul Haq DeepRusafa Binte HassanB. Electrical and Electronic Engineerin

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Polarity Control at Runtime:from Circuit Concept to Device Fabrication

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology

Electron-electron interaction driven phenomena in carbon nanotube devices

CNTs also offer new opportunities to study new science and develop new technology enabled by their strong electron-electron (e-e) interactions. The lack of dielectric screening inherent in nanoscale structures like CNTs leads to strong e-e interactions, which produce unique physical phenomena. In this thesis, we study the effects of strong e-e interactions in CNTs through the experimental system of suspended CNT devices fabricated with two gate electrodes. The work presented here includes the development of a theoretical framework to understand of the behavior of these ‘split-gate’ devices. Using this framework, we are able observe signatures of the strong e-e interactions in CNTs.The purpose of using split-gates (two gate electrodes) is to electrostatically dope the CNT into a pn junction. These suspended CNT pn junctions have been used by several groups to investigate the optoelectronic properties of CNTs. However, the device transport models proposed by previous authors have been unable to explain the disparities in experimental observations. In particular, different authors have seen different responses of the source-drain current vs source-drain bias (Isd-Vsd characteristic) of similar devices. To explore the reason for this variability, we investigate the Isd-Vsdcharacteristic while varying the metal contact work function. The results allow us to develop a model that explains the variation in the literature in terms of variations in the metal work functions and or CNT diameter. The device is modeled with a pn junction diode in the center of the CNT and Schottky diodes at the contacts. We are also able to use this model and temperature dependent measurements to extract the n-type and p-type Schottky barrier heights.Carbon nanotubes (CNTs) are a promising material for high-performance electronics beyond silicon. Unlike silicon, the nature of the transport band gap in CNTs is not fully understood. The transport gap in CNTs is predicted to be strongly driven by e-e interactions and correlations, even at room temperature. The effects a dielectric material, like a SiO2 substrate, on the transport gap is important for implementation of this technology. Here, we use dielectric liquids to screen e-e interactions in individual suspended ultra-clean CNTs. Using multiple techniques, the transport gap is measured as dielectric screening is increased. Changing the dielectric environment from air to isopropanol, we observe a 25% reduction in the transport gap of semiconducting CNTs, and a 32% reduction in the band gap of narrow-gap CNTs. Additional measurements are reported in dielectric oils. Our results elucidate the nature of the transport gap in CNTs, and show that dielectric environment offers a mechanism for significant control over the transport band gap.CNTs are candidates for next-generation photovoltaic technology, because they have the potential to break the Shockley-Queisser limit. Because of the strong e-e interactions, photogenerated carriers in CNTs can undergo carrier multiplication, where more than one electron-hole pair is created per absorbed photon. The photocurrent quantum yield(PCQY), defined as the number of electron-hole pairs extracted from a device per absorbed photon should therefore be able to exceed unity. However, a previous measurement on a similar split-gate device only achieved PCQY of 1-5%. To address this discrepancy we study photocurrent generation in individual suspended carbon nanotube pn junctions using spectrally resolved scanning photocurrent microscopy. Spatial maps of the photocurrent allow us to determine the length of the p–n junction intrinsic region, as well as the role of the n-type Schottky barrier. We show that reverse-bias operation eliminates complications caused by the n-type Schottky barrier and increases the length of the intrinsic region. We develop a method of determining the PCQY that takes into account the beam waist, length of the intrinsic region, CNT diameter, resonant absorption cross section of CNTs, and intensity enhancement from reflection off the substrate. We find that the room temperature PCQY is approximately 30% when exciting the carbon nanotube at the S44 and S55 excitonic transitions. The PCQY value is an order of magnitude larger than previous estimates.Keywords: device physics, electron-electron interactions, carbon nanotube

Schottky Field Effect Transistors and Schottky CMOS Circuitry

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a bulk switching SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an increase in current injection with minimal process complexity. The different switching mechanism realized with this technique also reduces the ambipolar leakage current that has so often plagued SFETs of more conventional design. In addition, these devices have been utilized in a patent pending approach that may facilitate an increase in circuit density for devices of a given size. In other words, for example, it may be possible to achieve circuit density equivalent to 65 nm technology using a 90 nm process, while at the same time preserving or reducing local interconnect density for enhanced overall system speed. Fabrication details and electrical results will be discussed, as well as some initial modeling efforts toward gaining insight into the details of current injection at the metal-semiconductor (M-S) interface. The challenges faced using the ITS approach at aggressive scales will be discussed, as will the potential advantages and disadvantages of other approaches to SFET technology

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications