Sensitivity Analysis and Distortion Decomposition of Mildly Nonlinear Circuits

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level

Time-Varying Volterra Analysis of Nonlinear Circuits

Today’s advances in communication systems and VLSI circuits increases the performance requirements and complexity of circuits. The performance of RF and mixed-signal circuits is normally limited by the nonlinear behavior of the transistors used in the design. This makes simulation of nonlinear circuits more important. Volterra series is a method used for simulation of mildly nonlinear circuits. Using Volterra series the response of the nonlinear circuit is converted into a sum of multiple linear circuit responses. Thus, using Volterra series, simulation of nonlinear circuits in frequency-domain analysis becomes possible. However, Volterra series is not able to simulate strongly nonlinear circuits such as saturated Power Amplifiers. In this thesis, a new time-varying Volterra analysis is presented. The time-varying Volterra analysis is the generalization of conventional Volterra analysis where instead of using a DC expansion point a time-varying waveform has been used. Employing a time-varying expansion waveform for Volterra analysis, time-varying Volterra achieves better accuracy than conventional Volterra. The time-varying expansion waveforms are derived using a fast pre-analysis of the circuit. Using numerical examples, it has been shown that the time-varying Volterra is capable of simulating nonlinear circuits with better accuracy than conventional Volterra analysis. The time-varying Volterra analysis in both time and frequency domains are discussed in this thesis. The time-varying Volterra analysis has been used to simulate a saturated Class-F Power Amplifier in frequency-domain. The simulation results show good agreement with ELDO® steady-state and Harmonic Balance simulation results. The proposed method manages to simulate nonlinear circuits, such as saturated Power Amplifier, mixers and nonlinear microwave circuits, with good accuracy. Also, this method can be used to simulate circuit with large number of nonlinear elements without the convergence issues of Harmonic Balance

Fast Simulation of Analog Circuit Blocks under Nonstationary Operating Conditions

This paper proposes a black-box behavioral modeling framework for analog circuit blocks operating under small-signal conditions around non-stationary operating points. Such variations may be induced either by changes in the loading conditions or by event-driven updates of the operating point for system performance optimization, e.g., to reduce power consumption. An extension of existing data-driven parameterized reduced-order modeling techniques is proposed that considers the time-varying bias components of the port signals as non-stationary parameters. These components are extracted at runtime by a lowpass filter and used to instantaneously update the matrices of the reduced-order state-space model realized as a SPICE netlist. Our main result is a formal proof of quadratic stability of such Linear Parameter Varying (LPV) models, enabled by imposing a specific model structure and representing the transfer function in a basis of positive functions whose elements constitute a partition of unity. The proposed quadratic stability conditions are easily enforced through a finite set of small-size Linear Matrix Inequalities (LMI), used as constraints during model construction. Numerical results on various circuit blocks including voltage regulators confirm that our approach not only ensures the model stability, but also provides speedup in runtime up to 2 orders of magnitude with respect to full transistor-level circuits

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Parameterized macromodeling of passive and active dynamical systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

Spectral methods for circuit analysis

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 119-124).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Harmonic balance (HB) methods are frequency-domain algorithms used for high accuracy computation of the periodic steady-state of circuits. Matrix-implicit Krylov-subspace techniques have made it possible for these methods to simulate large circuits more efficiently. However, the harmonic balance methods are not so efficient in computing steady-state solutions of strongly nonlinear circuits with rapid transitions. While the time-domain shooting-Newton methods can handle these problems, the low-order integration methods typically used with shooting-Newton methods are inefficient when high solution accuracy is required. We first examine possible enhancements to the standard state-of-the-art preconditioned matrix-implicit Krylovsubspace HB method. We formulate the BDF time-domain preconditioners and show that they can be quite effective for strongly nonlinear circuits, speeding up the HB runtimes by several times compared to using the frequency-domain block-diagonal preconditioner. Also, an approximate Galerkin HB formulation is derived, yielding a small improvement in accuracy over the standard pseudospectral HB formulation, and about a factor of 1.5 runtime speedup in runs reaching identical solution error. Next, we introduce and develop the Time-Mapped Harmonic Balance method (TMHB) as a fast Krylov-subspace spectral method that overcomes the inefficiency of standard harmonic balance for circuits with rapid transitions. TMHB features a non-uniform grid and a time-map function to resolve the sharp features in the signals. At the core of the TMHB method is the notion of pseudo Fourier approximations. The rapid transitions in the solution waveforms are well approximated with pseudo Fourier interpolants, whose building blocks are complex exponential basis functions with smoothly varying frequencies. The TMHB features a matrix-implicit Krylov-subspace solution approach of same complexity as the standard harmonic balance method. As the TMHB solution is computed in a pseudo domain, we give a procedure for computing the real Fourier coefficients of the solution, and we also detail the construction of the time-map function. The convergence properties of TMHB are analyzed and demonstrated on analytic waveforms. The success of TMHB is critically dependent on the selection of a non-uniform grid. Two grid selection strategies, direct and iterative, are introduced and studied. Both strategies are a priori schemes, and are designed to obey accuracy and stability requirements. Practical issues associated with their use are also addressed. Results of applying the TMHB method on several circuit examples demonstrate that the TMHB method achieves up to five orders of magnitude improvement in accuracy compared to the standard harmonic balance method. The solution error in TMHB decays exponentially faster than the standard HB method when the size of the Fourier basis increases linearly. The TMHB method is also up to six times faster than the standard harmonic balance method in reaching identical solution accuracy, and uses up to five times less computer memory. The TMHB runtime speedup factor and storage savings favorably increase for stricter accuracy requirements, making TMHB well suited for high accuracy simulations of large strongly nonlinear circuits with rapid transitions.by Ognen J. Nastov.Ph.D

Circuit Design

Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects

Design techniques for low-power SAR ADCs in nano-scale CMOS technologies

This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin

SCEE 2008 book of abstracts : the 7th International Conference on Scientific Computing in Electrical Engineering (SCEE 2008), September 28 – October 3, 2008, Helsinki University of Technology, Espoo, Finland

This report contains abstracts of presentations given at the SCEE 2008 conference.reviewe