Advanced modulation technology development for earth station demodulator applications

The purpose of this contract was to develop a high rate (200 Mbps), bandwidth efficient, modulation format using low cost hardware, in 1990's technology. The modulation format chosen is 16-ary continuous phase frequency shift keying (CPFSK). The implementation of the modulation format uses a unique combination of a limiter/discriminator followed by an accumulator to determine transmitted phase. An important feature of the modulation scheme is the way coding is applied to efficiently gain back the performance lost by the close spacing of the phase points

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

TDRSS telecommunications study. Phase 1: Final report

A parametric analysis of the telecommunications support capability of the Tracking and Data Relay Satellite System (TDRSS) was performed. Emphasis was placed on maximizing support capability provided to the user while minimizing impact on the user spacecraft. This study evaluates the present TDRSS configuration as presented in the TDRSS Definition Phase Study Report, December 1973 to determine potential changes for improving the overall performance. In addition, it provides specifications of the user transponder equipment to be used in the TDRSS

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Supply modulated GaN HEMT power amplifiers - From transistor to system

Power amplifiers (PAs) for mobile communication applications are required to fulfil stringent requirements concerning linearity while keeping a high efficiency over a wide power range and bandwidth. To achieve this, a number of advanced PA topologies have been developed, mostly based on either load modulation, such as Doherty PAs or load modulation balanced PAs, or on supply modulation such as envelope tracking or envelope elimination and restoration. Supply modulation has an advantage over other topologies as the power range of high efficiency can be realised over arbitrary bandwidths, only limited by the bandwidth of the PA. This does, however, come at the cost of a significantly more complicated voltage supply. Instead of a static supply voltage, the PA needs to be provided with one which is rapidly changing, requiring a supply modulator capable of powering the PA while modulating its supply voltage. This thesis investigates a number of challenges in supply modulated power amplifiers, ranging from the transistor itself to circuit design and system level considerations and focusses on power levels up to 10 W and frequencies between 1 GHz and 4 GHz. Transistors, as the centre-piece of a PA, determine how well the PA reacts to a changing supply voltage. In this work, the traits that make GaN HEMTs suitable for supply modulated PAs were investigated, and gain variation with changing supply voltage was established as an important parameter. This gain variation is described in detail and its impacts on PA performance are discussed. By comparing transistors in literature, gain variation has been demonstrated to be a prevalent characteristic in transistors with GaN HEMTs showing a very wide range of gain variation. Using a small-signal model based on measurements, the voltage dependent behaviour of the feedback capacitance CGD is, for the first time, identified as the origin of small-signal gain variation. This is traced down to the gate field plate which is commonly used to combat surface trapping effects in GaN HEMTs. With this in mind, two different ways of changing the transistor geometry to reduce the impact of gain variation and thus optimise the transistor for operation in supply modulated PAs are discussed and demonstrated using a 250 nm GaN HEMT. As a result of the non-linearity of the feedback and gate-source capacitances, the input impedance of GaN HEMTs changes with supply voltage and drive power. This prevents the transistor from being matched at all supply voltages and input powers and introduces phase distortion. Using simulation and measurement, the impact of input impedance on linearity and efficiency of supply modulated power amplifiers is demonstrated on a 2.9 GHz 10 W PA. Careful selection of the input impedance allows improvement of AM/PM distortion of a supply modulated PA with little cost in terms of AM/AM and PAE. I Supply modulators have a significant impact on efficiency and linearity of the ET system. One supply modulator topology with the potential to generate a supply voltage with a high modulation bandwidth is the RF modulator in which the input DC voltage is turned into an RF signal and rectified, resulting in an output voltage which depends on the excitation of the PA. While PAs are well understood in every detail, there are gaps in the understanding of RF rectifiers. Using active load-pull/source-pull measurements, intrinsic gate and drain waveforms of a GaN HEMT operated as a rectifier are demonstrated for the first time. This allows in-detail evaluation of the impact of the gate termination in self-synchronous rectifiers. It also allows detailed analysis of the loss mechanisms in rectifiers and formulation of the required impedances to realise efficient self-synchronous operation, resulting in efficiencies exceeding 90% over wide power ranges. Using waveform engineering, a new type of RF modulator, with potentially very high bandwidths, based on even harmonic generation/injection is proposed. The necessary operating conditions of the rectifier part of the modulator are emulated using an active load-pull/source-pull system to successfully demonstrate that the rectifier behaves as predicted. Using a simple demonstrator, preliminary measurements were conducted and the RF modulator was shown to work, reaching efficiencies up to 78%. As PA and supply modulator are combined, they present impedances to each other. These impedances have a significant impact on the behaviour of both sub-systems. A simple way to characterise both the impedance presented to the PA by the modulator and the impedance presented to the modulator by the PA is described. Using a state-of-the-art modulator, these impedances are measured, the modulator impedance is demonstrated to be close to the simulated value. These measurements also demonstrate that the impedances change significantly with the operating conditions