Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility

The purpose of this investigation is to demonstrate value for Auto Defect Classification (ADC) for patterned wafer inspection systems within a high volume manufacturing fabrication in the Process Limited Yield (PLY) defect area. Process excursions in all functional Unit Process (UP) areas, examples are of etch, litho, diffusion, are monitored by PLY. Troubleshooting of process excursions using added defect density count with a small percentage (random or largest 50 examples) of and inline Scanning Electron Microscope (SEM) data classification review does not give a clear indication of the full wafer data. Statistical Process Control (SPC) trigging on total counts or defect density is not as powerful as making excursion decisions on classified data from ADC (Fisher, 2002). The ADC data gives classification of the entire wafer rather than a smaller sample making signature analysis to be an additional troubleshooting tool. The inline ADC data does not have near the resolution of the SEM but can be used to help make important decisions to what is occurring in the manufacturing line. The interest is to gain a full understanding of the current capabilities and limitation of ADC and to apply the learning to enable faster reaction and visibility into process and tool excursions within a high volume manufacturing fabrication. The Technical Learning Vehicle (TLV), high running product layer at the leading design rule, there were approximately 10,000 wafers a week with 1000 wafer die (chips) per wafer. A sustained improvement in yield of 1% across the entire manufacturing line would equate to almost 1 million dollars a month of saving. With the ability to tightly control multiple etch process tools, the resulting yield improvement was 3% across 15% of the line. With the baseline yield improvement along with ability to react quickly to process excursions, the combined improvement resulted in excessive of 5 million dollar a year of reoccurring savings

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

High-Speed Low-Voltage Line Driver for SerDes Applications

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps

Intelligent shop scheduling for semiconductor manufacturing

Semiconductor market sales have expanded massively to more than 200 billion dollars annually accompanied by increased pressure on the manufacturers to provide higher quality products at lower cost to remain competitive. Scheduling of semiconductor manufacturing is one of the keys to increasing productivity, however the complexity of manufacturing high capacity semiconductor devices and the cost considerations mean that it is impossible to experiment within the facility. There is an immense need for effective decision support models, characterizing and analyzing the manufacturing process, allowing the effect of changes in the production environment to be predicted in order to increase utilization and enhance system performance. Although many simulation models have been developed within semiconductor manufacturing very little research on the simulation of the photolithography process has been reported even though semiconductor manufacturers have recognized that the scheduling of photolithography is one of the most important and challenging tasks due to complex nature of the process. Traditional scheduling techniques and existing approaches show some benefits for solving small and medium sized, straightforward scheduling problems. However, they have had limited success in solving complex scheduling problems with stochastic elements in an economic timeframe. This thesis presents a new methodology combining advanced solution approaches such as simulation, artificial intelligence, system modeling and Taguchi methods, to schedule a photolithography toolset. A new structured approach was developed to effectively support building the simulation models. A single tool and complete toolset model were developed using this approach and shown to have less than 4% deviation from actual production values. The use of an intelligent scheduling agent for the toolset model shows an average of 15% improvement in simulated throughput time and is currently in use for scheduling the photolithography toolset in a manufacturing plant

Optimization Studies for the COBRA Neutrinoless Double-Beta Decay Experiment and Results from a Prototype

The COBRA experiment uses Cadmium Zinc Telluride: CZT) room-temperature semiconductor detectors to search for the neutrinoless double-beta decay of cadmium-116. While the experiment has produced globally competitive half-life limits with data from coplanar-grid CZT detectors, a future ton-scale iteration could set limits constraining the effective Majorana neutrino mass to less than 100 meV. The aim of this work is to determine the optimal CZT detector type for such an experiment. First, an overview of the relevant neutrino physics as well as an introduction to the COBRA experiment is presented. The performance characteristics and design criteria for CZT detectors are then covered, both in general and as they relate to COBRA. Simulations and prototype experiments have been performed using two of the detector design candidates. The method and results are discussed in detail. Finally, the prototype is compared with other CZT detector designs in the context of performance and scalability for a 420 kg COBRA experiment

VLSI Revisited - Revival in Japan

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government - through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors, Hitachi, Sony, Toshiba, Elpida, Renesas, Sematech, VLSI, JESSI, MEDEA, ASPLA, MIRAI, innovation system

VLSI REVISITED – REVIVAL IN JAPAN

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government – through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors; Hitachi; Sony; Toshiba; Elpida; Renesas; Sematech; VLSI; JESSI; MEDEA; ASPLA; MIRAI; innovation system