Time-efficient fault detection and diagnosis system for analog circuits

Time-efficient fault analysis and diagnosis of analog circuits are the most important prerequisites to achieve online health monitoring of electronic equipments, which are involving continuing challenges of ultra-large-scale integration, component tolerance, limited test points but multiple faults. This work reports an FPGA (field programmable gate array)-based analog fault diagnostic system by applying two-dimensional information fusion, two-port network analysis and interval math theory. The proposed system has three advantages over traditional ones. First, it possesses high processing speed and smart circuit size as the embedded algorithms execute parallel on FPGA. Second, the hardware structure has a good compatibility with other diagnostic algorithms. Third, the equipped Ethernet interface enhances its flexibility for remote monitoring and controlling. The experimental results obtained from two realistic example circuits indicate that the proposed methodology had yielded competitive performance in both diagnosis accuracy and time-effectiveness, with about 96% accuracy while within 60 ms computational time.Peer reviewedFinal Published versio

Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Mapping constrained optimization problems to quantum annealing with application to fault diagnosis

Current quantum annealing (QA) hardware suffers from practical limitations such as finite temperature, sparse connectivity, small qubit numbers, and control error. We propose new algorithms for mapping boolean constraint satisfaction problems (CSPs) onto QA hardware mitigating these limitations. In particular we develop a new embedding algorithm for mapping a CSP onto a hardware Ising model with a fixed sparse set of interactions, and propose two new decomposition algorithms for solving problems too large to map directly into hardware. The mapping technique is locally-structured, as hardware compatible Ising models are generated for each problem constraint, and variables appearing in different constraints are chained together using ferromagnetic couplings. In contrast, global embedding techniques generate a hardware independent Ising model for all the constraints, and then use a minor-embedding algorithm to generate a hardware compatible Ising model. We give an example of a class of CSPs for which the scaling performance of D-Wave's QA hardware using the local mapping technique is significantly better than global embedding. We validate the approach by applying D-Wave's hardware to circuit-based fault-diagnosis. For circuits that embed directly, we find that the hardware is typically able to find all solutions from a min-fault diagnosis set of size N using 1000N samples, using an annealing rate that is 25 times faster than a leading SAT-based sampling method. Further, we apply decomposition algorithms to find min-cardinality faults for circuits that are up to 5 times larger than can be solved directly on current hardware.Comment: 22 pages, 4 figure

Surface Defect Classification for Hot-Rolled Steel Strips by Selectively Dominant Local Binary Patterns

Developments in defect descriptors and computer vision-based algorithms for automatic optical inspection (AOI) allows for further development in image-based measurements. Defect classification is a vital part of an optical-imaging-based surface quality measuring instrument. The high-speed production rhythm of hot continuous rolling requires an ultra-rapid response to every component as well as algorithms in AOI instrument. In this paper, a simple, fast, yet robust texture descriptor, namely selectively dominant local binary patterns (SDLBPs), is proposed for defect classification. First, an intelligent searching algorithm with a quantitative thresholding mechanism is built to excavate the dominant non-uniform patterns (DNUPs). Second, two convertible schemes of pattern code mapping are developed for binary encoding of all uniform patterns and DNUPs. Third, feature extraction is carried out under SDLBP framework. Finally, an adaptive region weighting method is built for further strengthening the original nearest neighbor classifier in the feature matching stage. The extensive experiments carried out on an open texture database (Outex) and an actual surface defect database (Dragon) indicates that our proposed SDLBP yields promising performance on both classification accuracy and time efficiencyPeer reviewe

Diagnosis of Frequency Response Analog Circuits using HHO-SVM

Monitoring the system, recognising when a fault has occurred, identifying the kind of defect and where it is located are all aspects of fault detection and isolation. To assess whether a problem has arisen inside a certain channel or region of operation, fault detection is used. For many technological processes in the creation of effective and safe advanced supervision systems, fault detection and diagnosis have grown in significance. This article's main goal is to increase the accuracy of faults detection in frequency response analogue circuits and execution of work needs to be speed up. For this purpose, two optimization techniques are used. One is grey wolf optimization (GWO) for the process of feature extraction and secondly Harris Hawk optimization (HHO) as classifier optimizer.   the features and optimize the classifier. The Sallen key circuit (SKC) are utilized for processing the input data. The filters like low pass, high pass and bandpass are designed based on SKC and optimized using GWO. Finally, the optimized features obtained from different circuits are fed to support vector machine classifier to identify the fault accuracy in the circuit. The SVM classifier is optimized using HHO to achieve best accurate output. The suggested technique with a low-dimensional feature optimisation and optimised classifier performed better than the prior methods according to simulation findings, and computing time was also greatly minimised

Application of artificial intelligence techniques to probeless fault diagnosis of printed circuit boards

This thesis describes investigations which led to the development of a failure diagnosis expert system for printed circuit boards which exploits functional test data. The boards considered are highly complex mixed signal (analogue and digital) systems. The data is output from automatic test equipment which is used to test every board subsequent to manufacture.The use of a conventional machine learning technique produced only limited success due to the very large search space of failure reports. This also ruled out the use of some conventional knowledge-based approaches. In addition, there was a requirement to track changes m printed circuit board design and manufacture which also ruled out some techniques.Our investigations lead to the development of a system which tracks changes by learning in a more restricted search space derived from the original space of reports. The system performs a diagnosis by matching a failure report with information about previously seen reports. Both exact and inexact matching were investigated. The matching rules used are heuristic. The system also uses basic circuit connectivity information in conjunction with the matching procedure to improve diagnostic performance especially in cases where matching fails to identify a unique component