FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A New Design Methodology For Enhancing The Transient Loading Of Low Drop-out Regulators (LDRs)

A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 104 seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a

A New Design Methodology For Enhancing The Transient Loading Of Low Drop-out Regulators (LDRs)

A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 104 seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a

A fully-integrated 180 nm CMOS 1.2 V low-dropout regulator for low-power portable applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a -40 to 120 degrees C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (I-q = 8.6 mu A) and minimum area consumption (0.109 mm(2)) are maintained, including a reference voltage V-ref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns