A FPGA system for QRS complex detection based on Integer Wavelet Transform

Due to complexity of their mathematical computation, many QRS detectors are implemented in software and cannot operate in real time. The paper presents a real-time hardware based solution for this task. To filter ECG signal and to extract QRS complex it employs the Integer Wavelet Transform. The system includes several components and is incorporated in a single FPGA chip what makes it suitable for direct embedding in medical instruments or wearable health care devices. It has sufficient accuracy (about 95%), showing remarkable noise immunity and low cost. Additionally, each system component is composed of several identical blocks/cells what makes the design highly generic. The capacity of today existing FPGAs allows even dozens of detectors to be placed in a single chip. After the theoretical introduction of wavelets and the review of their application in QRS detection, it will be shown how some basic wavelets can be optimized for easy hardware implementation. For this purpose the migration to the integer arithmetic and additional simplifications in calculations has to be done. Further, the system architecture will be presented with the demonstrations in both, software simulation and real testing. At the end, the working performances and preliminary results will be outlined and discussed. The same principle can be applied with other signals where the hardware implementation of wavelet transform can be of benefit

Optimization and implementation of the wavelet based algorithms for embedded biomedical signal processing

Existing biomedical wavelet based applications exceed the computational, memory and consumption resources of low-complexity embedded systems. In order to make such systems capable to use wavelet transforms, optimization and implementation techniques are proposed. The Real Time QRS Detector and De-noising Filter are developed and implemented in 16-bit fixed point microcontroller achieving 800 Hz sampling rate, occupation of less than 500 bytes of data memory, 99.06% detection accuracy, and 1 mW power consumption. By evaluation of the obtained results it is found that the proposed techniques render negligible degradation in detection accuracy of -0.41% and SNR of -2.8%, behind 2-4 times faster calculation, 2 times less memory usage and 5% energy saving. The same approach can be applied with other signals where the embedded implementation of wavelets can be beneficial

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

General rational approximation of Gaussian wavelet series and continuous-time gm-C filter implementation

© 2020 John Wiley & Sons, Ltd. This is the accepted version of the following article: Li, M, Sun, Y. General rational approximation of Gaussian wavelet series and continuous‐time g m ‐C filter implementation. Int J Circ Theor Appl. 2020; 1– 17., which has been published in final form at https://doi.org/10.1002/cta.2834.A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple gm-C integrators is presented in this work. Firstly, the multi-order derivatives of Gaussian function are analysed and proved as wavelet base functions. Then a high accuracy general approximation model of Gaussian wavelet series is constructed and the transfer function of first order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a 5th order continuous-time analogue first order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with simple gm-C integrator as the basic blocks. Finally, simulation results demonstrate the proposed method is an excellent way for the wavelet transform implementation. The designed first order derivative of Gaussian wavelet filter circuit operates from a 0.53V supply voltage and a bias current 2.5nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1nW. Moreover, the high accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.Peer reviewe

A Deep Learning-Based ECG Delineator: Evaluation and Comparison on Standard Databases

Several algorithms have been proposed for the automatic detection of the ECG characteristic waves, namely P wave, T wave and QRS complex, with particular focus on the localization of the R peaks. This Thesis aims to leverage the standard Convolutional Neural Network (CNN) to propose a new Deep Learning-based ECG delineator for the individuation of the P, R and T peaks

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal ECG system for personalized and remote cardiac health monitoring. The novelty of this work is four-fold. Firstly, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for ADC. Secondly, a novel on-the-fly PQRST Boundary Detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Thirdly, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourthly, the system is having the capability to reconfigure the proposed Low power ADC for low (8 bits) and high (12 bits) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patient’s data from PTBDB, CSEDB and in-house IIT Hyderabad DB (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180 nm technology resulting in 9.47W (@ 1 MHz) power consumption and occupying 1.74mm2 silicon area

Investigating the effects of an on-chip pre-classifier on wireless ECG monitoring

In past years, heart disease has been the leading cause of death in most developed countries. Timely detection of a heart condition is necessary in order to prevent life threatening situations. Even when the problem is not a heart condition, the activity of the heart can supply vital information, which makes its monitoring extremely important. A new approach to patient monitoring was taken recently by introducing wireless sensor networks into medical care. The capability of monitoring multiple patients at once makes such a system ideal for pre-hospital and in-hospital emergency care. The main problems associated with wireless sensor networks are power consumption and scaling. The power consumption is a problem due to the need for increased mobility of such a system, while scaling is of concern because a large number of nodes is desired in order to monitor more patients. This thesis addresses the power and bandwidth problems associated with monitoring patients using wireless networks by introducing another level of signal processing at each node. The goal is to design a digital circuit that would detect any abnormality in the ECG signal and enable the data transmission only if such has occurred. Reducing the amount of data being transmitted reduces the necessary bandwidth for each node and with the introduction of the proposed chip, the power consumption of each node is affected as well

Robust Algorithms for Unattended Monitoring of Cardiovascular Health

Cardiovascular disease is the leading cause of death in the United States. Tracking daily changes in one’s cardiovascular health can be critical in diagnosing and managing cardiovascular disease, such as heart failure and hypertension. A toilet seat is the ideal device for monitoring parameters relating to a subject’s cardiac health in his or her home, because it is used consistently and requires no change in daily habit. The present work demonstrates the ability to accurately capture clinically relevant ECG metrics, pulse transit time based blood pressures, and other parameters across subjects and physiological states using a toilet seat-based cardiovascular monitoring system, enabled through advanced signal processing algorithms and techniques. The algorithms described herein have been designed for use with noisy physiologic signals measured at non-standard locations. A key component of these algorithms is the classification of signal quality, which allows automatic rejection of noisy segments before feature delineation and interval extractions. The present delineation algorithms have been designed to work on poor quality signals while maintaining the highest possible temporal resolution. When validated on standard databases, the custom QRS delineation algorithm has best-in-class sensitivity and precision, while the photoplethysmogram delineation algorithm has best-in-class temporal resolution. Human subject testing on normative and heart failure subjects is used to evaluate the efficacy of the proposed monitoring system and algorithms. Results show that the accuracy of the measured heart rate and blood pressure are well within the limits of AAMI standards. For the first time, a single device is capable of monitoring long-term trends in these parameters while facilitating daily measurements that are taken at rest, prior to the consumption of food and stimulants, and at consistent times each day. This system has the potential to revolutionize in-home cardiovascular monitoring