Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques

FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

Portable High-definition Audio Spectrum Analyzer

The Portable High-definition Audio Spectrum Analyzer (PHASA) allows the user to visualize the audio frequency spectrum of an incoming line-level stereo audio signal. Upon pressing the touch screen spectrum graph, the PHASA displays the corresponding frequency and volume levels as well as crosshairs at the touched location. The PHASA features multiple left/right channel display modes— Left channel only, right channel only, both channels simultaneously, and the average between the two channels. The PHASA features multiple resolution display modes (standard-resolution and high-resolution) and multiple dynamics display modes (standard dynamics, averaging, and peak/hold). The PHASA accepts input audio via a 1/4 TRS jack and outputs via a 1/4 TRS jack. When activated, the output jack outputs a stereo white noise signal for measuring the frequency response of external equipment. This capability makes the PHASA a useful tool for frequency response characterization of audio equipment, which allows for more informed audio engineering design decisions

Design, Commissioning and Performance of the PIBETA Detector at PSI

We describe the design, construction and performance of the PIBETA detector built for the precise measurement of the branching ratio of pion beta decay, pi+ -> pi0 e+ nu, at the Paul Scherrer Institute. The central part of the detector is a 240-module spherical pure CsI calorimeter covering 3*pi sr solid angle. The calorimeter is supplemented with an active collimator/beam degrader system, an active segmented plastic target, a pair of low-mass cylindrical wire chambers and a 20-element cylindrical plastic scintillator hodoscope. The whole detector system is housed inside a temperature-controlled lead brick enclosure which in turn is lined with cosmic muon plastic veto counters. Commissioning and calibration data were taken during two three-month beam periods in 1999/2000 with pi+ stopping rates between 1.3*E3 pi+/s and 1.3*E6 pi+/s. We examine the timing, energy and angular detector resolution for photons, positrons and protons in the energy range of 5-150 MeV, as well as the response of the detector to cosmic muons. We illustrate the detector signatures for the assorted rare pion and muon decays and their associated backgrounds.Comment: 117 pages, 48 Postscript figures, 5 tables, Elsevier LaTeX, submitted to Nucl. Instrum. Meth.

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Crexens™: an expandable general-purpose electrochemical analyzer

2019 Fall.Includes bibliographical references.Electrochemical analysis has gained a great deal of attention of late due to its low-cost, easy-to-perform, and easy-to-miniaturize, especially in personal health care where accuracy and mobility are key factors to bring diagnostics to patients. According to data from Centers for Medicare & Medicaid Services (CMS) in the US, the share of health expenditure in the US has been kept growing in the past 3 decades and reached 17.9% of its overall Gross Domestic Product till 2016, which is equivalent to $10,348 for every person in the US per year. On the other hand, health care resources are often limited not only in rural area but also appeared in well-developed countries. The urgent need and the lack of health resource brings to front the research interest of Point-of-Care (PoC) diagnosis devices. Electrochemical methods have been largely adopted by chemist and biologist for their research purposes. However, several issues exist within current commercial benchtop instruments for electrochemical measurement. First of all, the current commercial instruments are usually bulky and do not have handheld feature for point-of-care applications and the cost are easily near$5,000 each or above. Secondly, most of the instruments do not have good integration level that can perform different types of electrochemical measurements for different applications. The last but not the least, the existing generic benchtops instruments for electrochemical measurements have complex operational procedures that require users to have a sufficient biochemistry and electrochemistry background to operate them correctly. The proposed Crexens™ analyzer platform is aimed to present an affordable electrochemical analyzerwhile achieving comparable performance to the existing commercial instruments, thus, making general electrochemical measurement applications accessible to general public. In this dissertation, the overall Crexens™ electrochemical analyzer architecture and its evolution are presented. The foundation of the Crexens™ architecture was derived from two separate but related research in electrochemical sensing. One of them is a microelectrode sensor array using CMOS for neurotransmitter sensing; the other one is a DNA affinity-based capacitive sensor for infectious disease, such as ZIKA. The CMOS microelectrode sensor array achieved a 320uM sensitivity for norepinephrine, whereas the capacitive sensor achieved a dynamic range of detection from 1 /uL to 105 /uL target molecules (20 to 2 million targets), which makes it be within the detection range in a typical clinical application environment. This dissertation also covers the design details of the CMOS microelectrode array sensor and the capacitive sensor design as a prelude to the development of the Crexens™ analyzer architecture. Finally, an expandable integrated electrochemical analyzer architecture (Crexens™) has been designed for mobile point-of-care (POC) applications. Electrochemical methods have been explored in detecting various bio-molecules such as glucose, lactate, protein, DNA, neurotransmitter, steroid hormone, which resulted in good sensitivity and selectivity. The proposed system is capable of running electrochemical experiments including cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), electrochemical capacitive spectroscopy (ECS), amperometry, potentiometry, and other derived electrochemical based tests. This system consist of a front-end interface to sensor electrodes, a back-end user interface on smart phone and PC, a base unit as master module, a low-noise add-on module, a high-speed add-on module, and a multi-channel add-on module. The architecture allows LEGO™-like capability to stack add-on modules on to the base-unit for performance enhancements in noise, speed or parallelism. The analyzer is capable of performing up to 1900 V/s CV with 10 mV step, up to 12 kHz EIS scan range and a limit of detection at 637 pA for amperometric applications with the base module. With high performance module, the EIS scan range can be extended upto 5 MHz. The limit of detection can be further improved to be at 333 fA using the low-noise module. The form factor of the electrochemical analyzer is designed for its mobile/point-of-care applications, integrating its entire functionality on to a 70 cm² area of surface space. A glutamine enzymatic sensor was used to valid the capability of the proposed electrochemical analyzer and turned out to give good linearity and reached a limit of detection at 50 uM

A SIX-PORT MEASUREMENT DEVICE FOR HIGH POWER MICROWAVE VECTOR NETWORK ANALYSIS

The changes experienced in technology due to the third industrial revolution have over the years contributed immensely to the development of efficient devices and systems. As a result, solutions have been provided to challenges encountered in the heating industry. However, higher efficiency and better performance has undoubtedly been highly sort after. This paper presents the complete industrial development of a new system of a microwave device for use in S-band networks (2.45 GHz ISM band in this application): a vector network analyzer (VNA). The VNA, which is designed based on the six-port measurement principle, provides accurate measurements of both magnitude and phase of the load reflection coefficient. The device is designed to have high power handling capabilities and works under the full operating conditions of high-power microwave generators. Initial measurements show that the device perform stable and can perform temperature-independent measurements over protracted periods. The system is suited for on-line monitoring and control of network parameters in industrial waveguide applications.

802.15.4 Low Intermediate Frequency Radio Receiver

This project involves the design, building, and testing of a low intermediate frequency 802.15.4 receiver that uses an FPGA to perform final demodulation to baseband

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin