A True 1V 1µW Biomedical Front End with Reconfigurable ADC for Self powered Smarter IoT Healthcare Systems

This work proposes an ultralow power highly linear analog front-end (AFE) with an input dynamic range from 200μVpp to 20mVpp. The system consists of a signal conditioning instrumentation amplifier (IA), two programmable gain amplifiers (PGA), a mixed signal automatic gain control (AGC), two sample and hold (S/H), a 10 bit successive approximation register (SAR) analog to digital converter (ADC), and a ΣΔ modulator with 10 bit effective number of bits (ENOB). A highly linear capacitively-coupled IA is achieved by increasing its feedback factor. Moreover, a transconductance (gm) cancellation technique is proposed for achieving a high common mode rejection ratio (CMRR). The conditioned signal is digitized using a SAR ADC for an input range of 200μVpp to 2mVpp, and, an opamp-shared ΣΔ ADC for an input range of 2mVpp to 20mVpp. The selection between the two ADCs is done by the AGC. The full system is designed using 1V supply in UMC 0.18μm CMOS technology. The AFE (IA and the two PGAs) achieves an overall linearity of more than 12 bits, for an input range of 200μVpp to 20mVpp while consuming 300nW with a bandwidth of 0.05 - 250Hz. The power consumption of the SAR ADC is 40nW while operating at a sampling frequency of 1KHz. The ΣΔ ADC consumes 300nW at a sampling frequency of 32KHz with an OSR of 32. The proposed system is intended to be powered by an energy scavenging circuit without compromising its own performance. The system was successfully tested for an ECG signal obtained from PTB database

A low noise amplifier suitable for biomedical recording analog front-end in 65nm CMOS technology

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area

Noise Efficient Integrated Amplifier Designs for Biomedical Applications

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Cmos Based Lensless Imaging Systems And Support Circuits

While much progress has been made in various fields of study in past few decades, leading to better understanding of science as well as better quality of life, the role of optical sensing has grown among electrical, chemical, optical, and other physical signal modalities. As an example, fluorescent microscopy has become one of the most important methods in the modern biology. However, broader implementation of optical sensing has been limited due to the expensive and bulky optical and mechanical components of conventional optical sensor systems. To address such bottleneck, this dissertation presents several cost-effective, compact approaches of optical sensor arrays based on solid state devices that can replace the conventional components. As an example, in chapter 2 we demonstrate a chip-scale (<1 mm2 ) sensor, the Planar Fourier Capture Array (PFCA), capable of imaging the far-field without any off-chip optics. The PFCA consists of an array of angle-sensitive pixels manufactured in a standard semiconductor process, each of which reports one component of a spatial two-dimensional (2D) Fourier transform of the local light field. Thus, the sensor directly captures 2D Fourier transforms of scenes. The effective resolution of our prototype is approximately 400 pixels. My work on this project [15] includes a circuit design and layout and the overall testing of the imaging system. In chapter 3 we present a fully integrated, Single Photon Avalanche Detector (SPAD) using only standard low- voltage (1.8V) CMOS devices in a 0.18m process. The system requires one highvoltage AC signal which alternately reverse biases the SPADs into avalanche breakdown and then resets with a forward bias. The proposed self-quenching circuit intrinsically suppresses after-pulse effects, improving signal to noise ratio while still permitting fine time resolution. The required high-voltage AC signal can be generated by resonant structures and can be shared across arrays of SPADs [24]. An ideal light sensor to provide the precise incident intensity, location, and angle of incoming photons is shown in chapter 4. Single photon avalanche diodes (SPADs) provide such desired high (single photon) sensitivity with precise time information, and can be implemented at a pixel scale to form an array to extract spatial information. Furthermore, recent work has demonstrated photodiode-based structures (combined with micro-lenses and diffraction gratings) that are capable of encoding both spatial and angular information of the incident light. In this chapter, we describe the implementation of such grating structure on SPAD to realize a pixel-scale angle-sensitive single photon avalanche diode (A-SPAD) using a standard CMOS process. While the underlying SPAD structure provides the high sensitivity, the diffraction gratings consisting of two sets of metal layers offers the angle-sensitivity. Such unique combination of the SPAD and the diffraction gratings expand the sensing dimensions to pave a path towards a lens-less 3-D imaging and a light-field timeof-flight imaging. In chapter 5, we present a 72 x 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3-D fluorescent life time imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, to reject high-powered UV stimulus, and to map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of incoming light, enabling 3-D localization at a micrometer scale. The chip presented in this work also integrates pixel-level counters as well as shared timing circuitry, and is implemented in conventional 180nm CMOS technology without any post-processing. Contact-based read- out from a revolving MEMS accelerometers is problematic therefore contactless (optical) read-out is preferred. The optical readout requires an image sensor to resolve nanometer-scale shifts of the MEMS image. Traditional imagers record on a rectangular grid which is not well-suited for efficiently imaging rotating objects due to the significant processing overhead required to translate Cartesian coordinates to angular position. Therefore, in chapter 6 we demonstrate a high-speed ( 1kfps), circular, CMOS imaging array for contact-less, optical measurement of rotating inertial sensors. The imager is designed for real-time optical readout and calibration of a MEMS accelerometer revolving at greater than 1000rpm. The imager uses a uniform circular arrangement of pixels to enable rapid imaging of rotational objects. Furthermore, each photodiode itself is circular to maintain uniform response throughout the entire revolution. Combining a high frame rate and a uniform response to motion, the imager can achieve sub-pixel resolution (25nm) of the displacement of micro scale features. In order to avoid fixed pattern noise arising from non-uniform routing within the array we implemented a new global shutter technique that is insensitive to parasitic capacitance. To ease integration with various MEMS platforms, the system has SPI control, on-chip bias generation, sub-array imaging, and digital data read-out. My work on this project [20] includes a circuit design and lay- out and some testing including, a FPGA based controller design of the imaging system. In the previous chapters, compact and cost effective imaging sys- tems have been introduced. Those imaging systems show great potential for wireless implantable systems. A power rectifier for the implant provides a volt- age DC power with a small inductor, for small volume, from a small AC voltage input. In the last chapter we demonstrate an inductively powered, orthogonal current-reuse multi-channel amplifier for power-efficient neural recording. The power rectifier uses the input swing as a self-synchronous charge pump, making it a fully passive, full-wave ladder rectifier. The rectifier supplies 10.37[MICRO SIGN]W at 1.224V to the multi-channel amplifier, which includes bias generation. The prototype device is fabricated in a TSMC 65nm CMOS process, with an active area of 0.107mm2 . The maximum measured power conversion efficiency (PCE) is 16.58% with a 184mV input amplitude. My work on this project [25] in- cludes the rectifier design and overall testing to combine "orthogonal currentreuse neural amplifier" designed by Ben Johnson

Régulateurs "Waterfall" : une nouvelle topologie énergétique pour l'électronique

Ce travail décrit une nouvelle topologie d'alimentation qui apporte des bénéfices aux dispositifs portables et aux composants électroniques à faible consommation. À l'autre extrémité du spectre, il serait également applicable aux systèmes à tension de bus plus élevée, tels que les panneaux solaires et les véhicules électriques, qui doivent décomposer des tensions plus élevées en domaines utilisables. La nouvelle topologie, que nous avons nommée Waterfall regulator, est décrite dans le présent travail et nommée ainsi pour ses caractéristiques saillantes rappelant une chute en cascade. Ce dispositif ouvre de nouvelles perspectives pour les systèmes à très basse consommation, basse tension et courant faible. Le mode de fonctionnement consiste à diviser une source d'alimentation brute en plusieurs domaines de tension, qui peuvent ensuite être utilisés pour alimenter les éléments individuels d'un système ou plusieurs unités indépendantes. Nous décrivons ici le premier rapport sur la réussite de la version de recyclage de l'énergie de ce nouveau système. Le dispositif se caractérise par une série de régulateurs de tension à faible chute et de circuits de déversement de courant (pass MOSFET). Le régulateur partage le courant qui traverse sa charge respective et complète le courant du stade suivant par un déversoir de courant, selon les besoins. Le contrôle s'effectue via une architecture de contrôle en cascade et peut être étendu à des périphériques d'ordre supérieur.This work described a new power supply topology that benefits portable device and low power electronics. At the other end of the spectrum, it is also applicable to higher bus voltage systems like solar panels and electric vehicles that must split higher voltages into usable domains. The new topology, which we named waterfall regulator, is describe herein and named as such for its salient features reminiscent of a waterfall. It opens up a new realm of possibilities for supra low power, low voltage and low current systems. The mode of operation consists of splitting a raw supply source into smaller voltage domains which can then be used for powering individual element of a system or powering multiple independent units. We describe here the first report of successful energy recycling version of this novel system. The devices are composed of a series of low dropout voltage regulators and current spillways circuits (pass MOSFET). The regulators share current passing thought their respective load and supplement current through a current spillway as required. Control is achieved through a cascade architecture and can be scaled up to higher order devices

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Interfaces neuronales CMOS haute résolution pour l'électrophysiologie et l'optogénétique en boucle fermée

L’avenir de la recherche sur les maladies du cerveau repose sur le développement de nouvelles technologies qui permettront de comprendre comment cet organe si complexe traite, intègre et transfère l’information. Parmi celles-ci, l’optogénétique est une technologie révolutionnaire qui permet d’utiliser de la lumière afin d’activer sélectivement les neurones du cortex d’animaux transgéniques pour observer leur effet dans un vaste réseau biologique. Ce cadre expérimental repose typiquement sur l’observation de l’activité neuronale de souris transgéniques, car elles peuvent exprimer une grande variété de gènes et de maladies et qu’elles sont peu couteuses. Toutefois, la plupart des appareils de mesure ou de stimulation optogénétique disponible ne sont pas appropriés, car ils sont câblés, trop lourds et/ou trop simplistes. Malheureusement, peu de systèmes sans fil existent, et ces derniers sont grandement limités par la bande passante requise pour transmettre les données neuronales, et ils ne fournissent pas de stimulation optogénétique multicanal afin de stimuler et observer plusieurs régions du cerveau. Dans les dispositifs actuels, l’interprétation des données neuronales est effectuée ex situ, alors que la recherche bénéficierait grandement de systèmes sans fil assez intelligents pour interpréter et stimuler les neurones en boucle fermée, in situ. Le but de ce projet de recherche est de concevoir des circuits analogiques-numériques d’acquisition et de traitement des signaux neuronaux, des algorithmes d’analyse et de traitement de ces signaux et des systèmes electro-optiques miniatures et sans fil pour : i) Mener des expériences combinant l’enregistrement neuronal et l’optogénétique multicanal haute résolution avec des animaux libres de leurs mouvements. ii) Mener des expériences optogénétiques synchronisées avec l’observation, c.-à-d. en boucle fermée, chez des animaux libres de leurs mouvements. iii) Réduire la taille, le poids et la consommation énergétique des systèmes optogénétiques sans fil afin de minimiser l’impact de la recherche chez de petits animaux. Ce projet est en 3 phases, et ses principales contributions ont été rapportées dans dix conférences internationales (ISSCC, ISCAS, EMBC, etc.) et quatre articles de journaux publiés ou soumis, ainsi que dans un brevet et deux divulgations. La conception d’un système optogénétique haute résolution pose plusieurs défis importants. Notamment, puisque les signaux neuronaux ont un contenu fréquentiel élevé (_10 kHz), le nombre de canaux sous observation est limité par la bande passante des transmetteurs sans fil (2-4 canaux en général). Ainsi, la première phase du projet a visé le développement d’algorithmes de compression des signaux neuronaux et leur intégration dans un système optogénétique sans fil miniature et léger (2.8 g) haute résolution possédant 32 canaux d’acquisition et 32 canaux de stimulation optique. Le système détecte, compresse et transmet les formes d’onde des potentiels d’action (PA) produits par les neurones avec un field programmable gate array (FPGA) embarqué à faible consommation énergétique. Ce processeur implémente un algorithme de détection des PAs basé sur un seuillage adaptatif, ce qui permet de compresser les signaux en transmettant seulement les formes détectées. Chaque PA est davantage compressé par une transformée en ondelette discrète (DWT) de type Symmlet-2 suivie d’une technique de discrimination et de requantification dynamique des coefficients. Les résultats obtenus démontrent que cet algorithme est plus robuste que les méthodes existantes tout en permettant de reconstruire les signaux compressés avec une meilleure qualité (SNDR moyen de 25 dB _ 5% pour un taux de compression (CR) de 4.2). Avec la détection, des CR supérieurs à 500 sont rapportés lors de la validation in vivo. L’utilisation de composantes commerciales dans des systèmes optogénétiques sans fil augmentela taille et la consommation énergétique, en plus de ne pas être optimisée pour cette application. La seconde phase du projet a permis de concevoir un système sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogénétique multicanal, permettant de réduire significativement la taille et la consommation énergétique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la première puce à être doté de ces deux fonctionnalités. Le SoC possède 10 canaux d’enregistrement et 4 canaux de stimulation optogénétique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referré à l’entré (IRN de 3.2 μVrms), ce qui permet de cibler différents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numérique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-échantillonnage (OSR _50) pour réduire sa consommation et possède une résolution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique réduisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numérique, comparativement à la méthode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 μW. Le SoC implémente un nouveau circuit de stimulation optique basé sur une source de courant de type cascode avec rétroaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intégré dans un système optogénétique sans fil et validé in vivo. À ce jour et en excluant ce projet, aucun système sans-fil ne fait de l’optogénétique en boucle fermée simultanément au suivi temps réel de l’activité neuronale. Une contribution importante de ce travail est d’avoir développé le premier système optogénétique multicanal qui est capable de fonctionner en boucle fermée et le premier à être validé lors d’expériences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisième phase du projet a visé la conception d’un SoC CMOS numérique, appelé neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC développé lors de la phase 2 ont été intégrés dans un système optogénétique sans fil. Le ND-IC possède 3 modules : 1) le détecteur de PA adaptatif, 2) le module de compression possédant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui réutilise les données générées par le module de détection et de compression pour réduire sa complexité. Un lien entre un canal d’enregistrement et un canal de stimulation est établi selon l’association de chaque PA à un neurone, grâce à la classification, et selon l’activité de ce neurone dans le temps. Le ND-IC consomme 56.9 μW et occupe 0.08 mm2 par canal. Le système pèse 1.05 g, occupe un volume de 1.12 cm3, possède une autonomie de 3h, et est validé in vivo.The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 μVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 μW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 μW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo