This work proposes an ultralow power highly linear analog front-end (AFE) with an input dynamic range from 200μVpp to 20mVpp. The system consists of a signal conditioning instrumentation amplifier (IA), two programmable gain amplifiers (PGA), a mixed signal automatic gain control (AGC), two sample and hold (S/H), a 10 bit successive approximation register (SAR) analog to digital converter (ADC), and a ΣΔ modulator with 10 bit effective number of bits (ENOB). A highly linear capacitively-coupled IA is achieved by increasing its feedback factor. Moreover, a transconductance (gm) cancellation technique is proposed for achieving a high common mode rejection ratio (CMRR). The conditioned signal is digitized using a SAR ADC for an input range of 200μVpp to 2mVpp, and, an opamp-shared ΣΔ ADC for an input range of 2mVpp to 20mVpp. The selection between the two ADCs is done by the AGC. The full system is designed using 1V supply in UMC 0.18μm CMOS technology. The AFE (IA and the two PGAs) achieves an overall linearity of more than 12 bits, for an input range of 200μVpp to 20mVpp while consuming 300nW with a bandwidth of 0.05 - 250Hz. The power consumption of the SAR ADC is 40nW while operating at a sampling frequency of 1KHz. The ΣΔ ADC consumes 300nW at a sampling frequency of 32KHz with an OSR of 32. The proposed system is intended to be powered by an energy scavenging circuit without compromising its own performance. The system was successfully tested for an ECG signal obtained from PTB database

Dutta, Asudeb

Naik, J

Patra, P

Yadav, K

Dutta, A

Name not available

See	discussions,	stats,	and	author	profiles	for	this	publication	at:	https://www.researchgate.net/publication/280878548
A	True	1V	1	µW	Biomedical	Front	End	with
Reconfigurable	ADC	for	Self	powered	Smarter	IoT
Healthcare	Systems
Conference	Paper	·	July	2015
CITATIONS
0
READS
78
1	author:
Pravanjan	Patra
Indian	Institute	of	Technology	Hyderabad
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A True 1V 1µW Biomedical Front End with
Reconfigurable ADC for Self powered Smarter IoT
Healthcare Systems
Pravanjan Patra, Kunal Yadav, Jairaj Naik, Ashudeb Dutta
Department of Electrical Engineering, Indian Institute of Technology Hyderabad, India-502205
Email: pravanjanpatra80@gmail.com;kunalyadav2@gmail.com; kr.jairaj.naik@gmail.com; asudeb dutta@iith.ac.in
Abstract—This work proposes an ultralow power highly linear
analog front-end (AFE) with an input dynamic range from
200µVpp to 20mVpp. The system consists of a signal condi-
tioning instrumentation amplifier (IA), two programmable gain
amplifiers (PGA), a mixed signal automatic gain control (AGC),
two sample and hold (S/H), a 10 bit successive approximation
register (SAR) analog to digital converter (ADC), and a Σ∆
modulator with 10 bit effective number of bits (ENOB). A
highly linear capacitively-coupled IA is achieved by increasing its
feedback factor. Moreover, a transconductance (gm) cancellation
technique is proposed for achieving a high common mode
rejection ratio (CMRR). The conditioned signal is digitized using
a SAR ADC for an input range of 200µVpp to 2mVpp, and,
an opamp-shared Σ∆ ADC for an input range of 2mVpp to
20mVpp. The selection between the two ADCs is done by the
AGC. The full system is designed using 1V supply in UMC
0.18µm CMOS technology. The AFE (IA and the two PGAs)
achieves an overall linearity of more than 12 bits, for an input
range of 200µVpp to 20mVpp while consuming 300nW with
a bandwidth of 0.05− 250Hz. The power consumption of the
SAR ADC is 40nW while operating at a sampling frequency
of 1KHz. The Σ∆ ADC consumes 300nW at a sampling
frequency of 32KHz with an OSR of 32. The proposed system
is intended to be powered by an energy scavenging circuit without
compromising its own performance. The system was successfully
tested for an ECG signal obtained from PTB database.
I. INTRODUCTION
The growing demand for a low power, miniature bio-
potential signal acquisition and digitization system is the
motivation for this work. Recent research shows that majority
of cardiac diseases are caused due to unhealthy habits e.g.
improper diet, meager exercise, etc. A patient-centric health-
care system, emphasizing on prevention of such diseases and
continuous monitoring, becomes most relevant in the present
scenario. For such a healthcare system a portable, light weight
and microscopic devices are in demand. The major bottleneck
in the design of these systems is it’s power consumption.
The power of the system can be scaled by using a higher
transconductance efficiency (gm/ID) of input devices and
lower supply voltage for a particular technology node. But
the supply voltage cannot be scaled below Vthn + Vthp as
switches will not be able to operate [1]. Further utilizing a
higher gm/ID of input transistor will result in lower linearity
in high gain stages. So a proper optimized value of gm/ID
is required for obtaining higher gain, linearity, output swing,
while rendering low noise and consuming less power [2].
The bio-potential signal amplitude varies from tens of µV
Fig. 1. Block diagram of the proposed acquisition system.
to tens of mV [3][4]. So acquisition system should have a
noise level below the minimum signal amplitude for faithful
digitization by the subsequent ADCs. The noise of the system
is majorly contributed by the IA. Moreover, the flicker noise
of IA dominates the overall noise, which in turn degrades
the signal to noise plus distortion ratio (SNDR) of the whole
system. The flicker noise can be decreased by increasing the
width (W) of input transistors (gm) [5] for a particular bias
current, which results in increase of parasitic capacitance.
The increase in the input referred noise in gain stages with
capacitive feedback is inversely proportional to the net input
capacitance [6]. To reduce the input referred noise a high
input capacitor has to be used which leads to a lower input
impedance. The input capacitor should be less than 100pF to
have an impedance higher than 5MΩ at 50Hz for power line
rejection [7]. For a given noise, the higher input amplitudes
have a higher SNDR if the gain is low. If higher gain is used for
input amplitudes in the range of 5mV − 10mV , the amplifier
output becomes nonlinear because the output swing goes out
of the linear range and hence degrades the SNDR of the AFE.
Hence a trade-off is required between power, noise, linearity
and the input impedance. The pseudo resistance also plays a
major role in contributing non-linearity. Thus for achieving a
high linearity, an output swing of 100mV is generally used [3].
In this paper two channels, one for high amplitude and other
for low amplitude signal conditioning are proposed shown in
Fig. 1 . The multiplexing is done through AGC. Signals above
1mV are digitized using a Σ∆ ADC and signals below 1mV
are digitized using SAR ADC. The AGC also controls the two
PGA’s as shown in Fig. 1. The IA and PGA are shared among
the two channels.
The rest of the paper is organized as follows. Section
II describes implementation of individual blocks Section III
describes the S/H, SAR and Σ∆ ADC. Section IV shows the
Fig. 2. Block diagram of instrumentation amplifier and programmable gain
amplifier. Here Cu = 0.5pF , M=10, Cg = 0.4pF and Cu1 = 0.4pF .
Fig. 3. Proposed improvised RFC amplifier for higher CMRR at lower
frequencies.
simulation results. Section V gives the conclusion.
II. IMPLEMENTATION OF INDIVIDUAL BLOCKS
A. Instrumentation Amplifier and Programmable Amplifier
The characteristics of an IA for biomedical signal acqui-
sition are as follows (1) A CMRR of greater than 70dB. (2)
An input impedance greater than 5MΩ at 50Hz (3) A high
pass filter for removing the baseline wandering. (4) A high
pass cutoff frequency lesser than 50mHz [8] (5) The low
pass cutoff is given by the UGB of the amplifier and the
closed loop gain. In this work, the gain of the IA is chosen
to be 10 to process a signal of 10mV as an output swing
of 100mV will give a high linearity. The Recycling Folded
cascode topology is used in IA [9]. This topology renders a
higher gain and gm compared to the folded cascode topology
for same power consumption. The differential gain for RFC is
given by (1) and respective common mode gain is given by (2).
The common mode gain of RFC with common mode feedback
is expressed as in (3). The use of lower gain in IA decreases
the CMRR as the differential gain is decreased. So to enhance
the CMRR, a gm cancellation technique is proposed on RFC
topology as shown in Fig. ??. The DC current flowing through
the transistors M3a/M4a is bypassed through M3c/M4c, which
decreases gm3. The expression for differential and common
mode gain for the proposed amplifier is given in (4) and (5)
respectively with CMFB.
AvDM = gm1a(K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9) (1)
AvCM =
gm1a(K − 1)
1 + gm0r0
∗ (gm5ro5(ro1a||ro3a)||gm7ro7ro9)
(2)
AvCM−CMFB =
gm1a(K − 1)
1 + gm0r0
∗ 1
gmcmfb
(3)
AV DM−proposed = gm1a(α∗K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9)
(4)
AV CM−CMFBproposed =
gm1a(α ∗K − 1)
1 + gm0r0
∗ 1
gmcmfb
(5)
The common mode reduction in bandwidth of IA can be
attributed to the introduction of a zero in the closed loop. The
location of the zero and poles for common mode feedback is
shown in (6).
H(s) =
sC1z2[1 +R1sC2 − gmcmfbR1]
[1 +R1(sC1 + sC2)][1 +
gmcmfbR1
R1sC2+1
+ sCLz2]
(6)
where the load capacitor is represented as CL and
z2 = R1||( 1
sC2
) (7)
Two PGA’s are used with a unity gain bandwidth higher
than lower cutoff frequency to avoid decrease in 3db bandwidth
with increase in gain. PGA’s gain is set by the capacitor ratios.
The PGA is implemented with RFC for K = 3 and α = 1.
The capacitor values are programmed by AGC for different
gains based on the input signal amplitude. The AGC consists
of a peak detector and a digital logic which calculates the peak
value and accordingly gain is set shown in Fig. 2.
1) Noise Analysis: The noise of the IA is contributed by
the modified RFC. The noise in RFC is generated by the flicker
noise from M3 and M9 transistors. The noise equation for the
RFC is shown in (8). In (8) µn and µp represents mobility
of NMOS and PMOS respectively. The noise of proposed
architecture is similar to RFC [9]. The major noise contribution
is by M1a, M1b, M3a, M3b and M9. The noise contributed by
M3b is higher compared to M3a in RFC because of current
multiplication. In proposed architecture the noise due to M3b
and M3a will reduce by α times but M3c contribution is
(1−α)∗K which adds up to same value. The noise contribution
due to M3c can be decreased by decreasing the gm3c and
decreasing the load current i.e. current through M9 and M10.
The noise of RFC and proposed architecture can be reduced
by choosing (1 < K < 3). The noise can also be reduced
by using source degeneration resistors for M3a and M3b. The
source degeneration resistors are neglected here to reduce the
area.
V 2f =
(
2 ∗Kp
CoxL1aW1a(1 +K) ∗ f
)
∗[
1 +K2
1 +K
+K∗KNµnCoxn
KPµpCoxp
(
L1a
L3a
)2(1+
W3a
W3b
)+
K − 1
K + 1
(
L1a
L9
)2
]
(8)
The total IA input referred noise power expression is shown in
(9). The first term is due to the pseudo resistor and the second
term is due to the capacitive feedback [6].
V 2in =
[[
1
sC1R1
]2
∗ V 2nres +
[
Cin + Cp + Cf
Cin
]2
∗ V 2f
]
(9)
B. Sample and Hold, Σ∆ ADC and SAR ADC
The signal from PGA is passed on to sample and hold
amplifier. There are two sample and hold in the proposed
system, one for SAR ADC operating at a sampling frequency
of 1 KHz, and the other for Σ∆ ADC operating at a sampling
frequency of 32 KHz [16]. For a signal swing of 100mV, the
10 bit SAR ADC achieves a 7 bit resolution. For signals of
amplitude greater than 2mVpp, a conventional discrete time
(DT) cascaded integrator feedback (CIFB) modulator with 2nd
order noise shaping is chosen with a reference voltage of
400mVpp Fig. 4. Owing to the fact that the integrator is the
most power hungry block of the SDM, twofold strategy was
employed to minimize the ADCs power consumption. The
integrator is implemented using the enhanced recyclic folded
cascode (ERFC) designed in 1V [10][11]. For DT Σ∆ ADC,
the use of transmission gates as switches require higher aspect
ratio for particular resistance which results in higher parasitic
capacitance. So to drive these switches, switch drivers are
required which consumes more power. The above constraint
can be avoided by using level shifted clock phases without
using transmission gates.
Fig. 4. Single ended representation of the fully differential opamp shared
DT Σ∆ ADC . The circuit renders 1st order noise shaping when only
components in black color are activated, and 2nd order noise shaping when the
components in dark red are also activated. Here CS1=0.67pF , CS2=2.02pF ,
CS fb=0.79pF , Ci1=4pF , and Vcm= 0.9V .
FOM1 =
Power(W ) ∗ 1012
2
SNR(dB)−1.76
6.02 ∗ 2 ∗BW (Hz)
pJ/Conv. (10)
III. RESULTS
The performance of proposed AFE is compared in Table
I. The linearity for lowest and highest values of input signal
to the system can be verified from THD in Table I. The
performance of Σ∆ ADC is compared in Table II. The FOM
is calculated by the expression (10), which explains the power
consumption per sample conversion. The common mode gain
is reduced by 20dB for 50Hz and 60Hz line can be verified
from Fig. 5. Frequency response of AFE with different gain
tuning is plotted in Fig. 6. An ECG signal of amplitude 1mV
is fed to the IA and the AGC performance was verified by
the output of the PGA as shown in Fig. 7. The resistance plot
Fig. 5. Comparison between common mode gains of the conventional and
the proposed amplifier.
Fig. 6. PGA gain reconfigurability.
of the pseudo resistor is given in Fig. 8. The FFT plot of the
output of the ADC for input of 20mVpp to AFE is plotted in
Fig. 9 for Σ∆ ADC and Fig. 10 for SAR ADC for an input
of 0.2mVpp.
IV. CONCLUSION
An ultra-Low power biomedical signal acquisition and
digitization is presented. The AFE does the work of filtering
and amplification with a linearity greater than 12bits. The AGC
controls the gain of the PGA such that the input to ADC is
100mV. Each block of AFE is designed for minimum power
using gm/ID methodology and hardware sharing and phase
level boosting is also implemented to minimize power con-
sumption of Σ∆ ADC. The required performance is achieved
with 1µW power..
(a) Input ECG signal (b) ECG output from AFE after fixing
appropriate gain through AGC.
Fig. 7. Input and output ECG plots.
Fig. 8. Resistance plot of pseudo resistor.
Fig. 9. Full system output power spectrum for a sinewave input of 20mVpp
processed by AFE, AGC, Sample and Hold and Σ∆ ADC, respectively.
Fig. 10. Full system output Spectrum for a sine wave input of 0.2mVpp
processed by AFE, AGC, Sample and Hold and SAR ADC.
TABLE I. PERFORMANCE OF THE PROPOSED AFE
Parameter Value
This work [5],2006 [14],2012 [15],2013
Technology (µm) 0.18 0.35 0.13 0.13
Voltage Supply (V) 1 1 1 1.5
Midband Gain (dB) 20-60 40.2 40 40
Bandwidth (Hz) 0.5-250 0.003-245 0.4-8.5K 19.9K
Input 6µVrms 2.7µVrms 3.2µVrms 3.7µVrms
Referred for for
Noise (0.05-250Hz) (0.05-250Hz)
NEF 3.32 - 4.5 3.04
Offset(3σ) 500 µV - - -
CMRR @50Hz (dB) 75 61-64 >60 >78
PSRR (dB) 77 62-63 >60 >80
0.057% 0.053% 1.5% 1%
@ 20mVpp @ 5mVpp @ 1mVpp 16.5mVpp
THD 0.067% @ 16Hz
@ 2mVpp
0.1%
@ 0.2mVpp
Current
Consumption (A) 300n 330n 12.5µ 2.6µ
REFERENCES
[1] Dessouky, M.; Kaiser, A., ”Very low-voltage digital-audio Σ∆ modulator
with 88-dB dynamic range using local switch bootstrapping,” Solid-State
TABLE II. PERFORMANCE OF THE Σ∆ ADC
Parameter Value
This work [12] [?]
Technology (µm) 0.18 0.18 0.18
Voltage Supply (V) 1 0.9 0.7
Order 2nd 2nd 2nd
Bandwidth (Hz) 500 10k 8k
Fs (MHz) 0.032 5 1.024
Power Consumption (µW ) 0.3 200 80
Dynamic Range (dB) 76 83 75
FOM1 (pJ/Conv.) 0.58 0.866 1.087
Circuits, IEEE Journal of , vol.36, no.3, pp.349,355, Mar 2001.
[2] Wattanapanitch, W.; Fee, M.; Sarpeshkar, R., ”An Energy-Efficient
Micropower Neural Recording Amplifier,” Biomedical Circuits and Sys-
tems, IEEE Transactions on , vol.1, no.2, pp.136,147, June 2007.
[3] Xiaodan Zou; Xiaoyuan Xu; Libin Yao; Yong Lian, ”A 1-V 450-
nW Fully Integrated Programmable Biomedical Sensor Interface Chip,”
Solid-State Circuits, IEEE Journal of , vol.44, no.4, pp.1067,1077, April
2009.
[4] Qinwen Fan; Sebastiano, F.; Huijsing, J.H.; Makinwa, K.A.A., ”A 1.8W
60 nV/sqrt Hz Capacitively-Coupled Chopper Instrumentation Amplifier
in 65 nm CMOS for Wireless Sensor Nodes,” Solid-State Circuits, IEEE
Journal of , vol.46, no.7, pp.1534,1543, July 2011.
[5] Honglei Wu; Yong Ping Xu, ”A 1V 2.3/spl mu/W Biomedical Signal
Acquisition IC,” Solid-State Circuits Conference, 2006. ISSCC 2006.
Digest of Technical Papers. IEEE International , vol., no., pp.119,128,
6-9 Feb. 2006
[6] Steyaert, M.S.J.; Sansen, W.M.C., ”A micropower low-noise monolithic
instrumentation amplifier for medical purposes,” Solid-State Circuits,
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[7] Pallas-Areny, R., ”Interference-rejection characteristics of biopotential
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[8] Shuenn-Yuh Lee, Jia-Hua Hong, Jin-Ching Lee and Qiang Fang (2012).
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for portable ECG Detection Devices, Advances in Electrocardiograms-
Methods and Analysis, PhD. Richard Millis.
[9] Assaad, R.S.; Silva-Martinez, J., ”The Recycling Folded Cascode: A
General Enhancement of the Folded Cascode Amplifier,” Solid-State
Circuits, IEEE Journal of , vol.44, no.9, pp.2535,2542, Sept. 2009
[10] Patra, P.; Kumaravel, S.; Venkatramani, B., ”An enhanced fully dif-
ferential Recyclic Folded Cascode OTA,” Systems, Signals and Devices
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20-23 March 2012.
[11] Patra, P.; Jha, P.K.; Dutta, A., ”An enhanced recycling folded cas-
cade OTA with a positive feedback,” Microelectronics and Electronics
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search in , vol., no., pp.153,157, 19-21 Dec. 2013.
[12] Goes, J.; Vaz, B.; Monteiro, R.; Paulino, N., ”A 0.9V /spl Delta//spl
Sigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase
Technique,” Solid-State Circuits Conference, 2006. ISSCC 2006. Digest
of Technical Papers. IEEE International , vol., no., pp.191,200, 6-9 Feb.
2006.
[13] Sauerbrey, J.; Tille, T.; Schmitt-Landsiedel, D.; Thewes, R., ”A 0.7V
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[14] Fan Zhang; Holleman, J.; Otis, B.P., ”Design of Ultra-Low
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[15] M. Young, The Technical Writer’s Handbook. Mill Valley, CA: Uni-
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[16] Dai Zhang; Bhide, A.; Alvandpour, A., ”A 53-nW 9.1-ENOB 1-kS/s
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Circuits, IEEE Journal of , vol.47, no.7, pp.1585,1593, July 2012


A true 1V 1µW biomedical front end with reconfigurable ADC for self powered smarter IoT healthcare systems

A True 1V 1µW Biomedical Front End with Reconﬁgurable ADC for Self powered Smarter IoT Healthcare Systems

See	discussions,	stats,	and	author	profiles	for	this	publication	at:	https://www.researchgate.net/publication/280878548
A	True	1V	1	µW	Biomedical	Front	End	with
Reconfigurable	ADC	for	Self	powered	Smarter	IoT
Healthcare	Systems
Conference	Paper	·	July	2015
READS
50
1	author:
Pravanjan	Patra
Indian	Institute	of	Technology	Hyderabad
13	PUBLICATIONS			3	CITATIONS			
SEE	PROFILE
All	in-text	references	underlined	in	blue	are	linked	to	publications	on	ResearchGate,
letting	you	access	and	read	them	immediately.
Available	from:	Pravanjan	Patra
Retrieved	on:	21	April	2016
A True 1V 1µW Biomedical Front End with
Reconfigurable ADC for Self powered Smarter IoT
Healthcare Systems
Pravanjan Patra, Kunal Yadav, Jairaj Naik, Ashudeb Dutta
Department of Electrical Engineering, Indian Institute of Technology Hyderabad, India-502205
Email: pravanjanpatra80@gmail.com;kunalyadav2@gmail.com; kr.jairaj.naik@gmail.com; asudeb dutta@iith.ac.in
Abstract—This work proposes an ultralow power highly linear
analog front-end (AFE) with an input dynamic range from
200µVpp to 20mVpp. The system consists of a signal condi-
tioning instrumentation amplifier (IA), two programmable gain
amplifiers (PGA), a mixed signal automatic gain control (AGC),
two sample and hold (S/H), a 10 bit successive approximation
register (SAR) analog to digital converter (ADC), and a Σ∆
modulator with 10 bit effective number of bits (ENOB). A
highly linear capacitively-coupled IA is achieved by increasing its
feedback factor. Moreover, a transconductance (gm) cancellation
technique is proposed for achieving a high common mode
rejection ratio (CMRR). The conditioned signal is digitized using
a SAR ADC for an input range of 200µVpp to 2mVpp, and,
an opamp-shared Σ∆ ADC for an input range of 2mVpp to
20mVpp. The selection between the two ADCs is done by the
AGC. The full system is designed using 1V supply in UMC
0.18µm CMOS technology. The AFE (IA and the two PGAs)
achieves an overall linearity of more than 12 bits, for an input
range of 200µVpp to 20mVpp while consuming 300nW with
a bandwidth of 0.05− 250Hz. The power consumption of the
SAR ADC is 40nW while operating at a sampling frequency
of 1KHz. The Σ∆ ADC consumes 300nW at a sampling
frequency of 32KHz with an OSR of 32. The proposed system
is intended to be powered by an energy scavenging circuit without
compromising its own performance. The system was successfully
tested for an ECG signal obtained from PTB database.
I. INTRODUCTION
The growing demand for a low power, miniature bio-
potential signal acquisition and digitization system is the
motivation for this work. Recent research shows that majority
of cardiac diseases are caused due to unhealthy habits e.g.
improper diet, meager exercise, etc. A patient-centric health-
care system, emphasizing on prevention of such diseases and
continuous monitoring, becomes most relevant in the present
scenario. For such a healthcare system a portable, light weight
and microscopic devices are in demand. The major bottleneck
in the design of these systems is it’s power consumption.
The power of the system can be scaled by using a higher
transconductance efficiency (gm/ID) of input devices and
lower supply voltage for a particular technology node. But
the supply voltage cannot be scaled below Vthn + Vthp as
switches will not be able to operate [1]. Further utilizing a
higher gm/ID of input transistor will result in lower linearity
in high gain stages. So a proper optimized value of gm/ID
is required for obtaining higher gain, linearity, output swing,
while rendering low noise and consuming less power [2].
The bio-potential signal amplitude varies from tens of µV
Fig. 1. Block diagram of the proposed acquisition system.
to tens of mV [3][4]. So acquisition system should have a
noise level below the minimum signal amplitude for faithful
digitization by the subsequent ADCs. The noise of the system
is majorly contributed by the IA. Moreover, the flicker noise
of IA dominates the overall noise, which in turn degrades
the signal to noise plus distortion ratio (SNDR) of the whole
system. The flicker noise can be decreased by increasing the
width (W) of input transistors (gm) [5] for a particular bias
current, which results in increase of parasitic capacitance.
The increase in the input referred noise in gain stages with
capacitive feedback is inversely proportional to the net input
capacitance [6]. To reduce the input referred noise a high
input capacitor has to be used which leads to a lower input
impedance. The input capacitor should be less than 100pF to
have an impedance higher than 5MΩ at 50Hz for power line
rejection [7]. For a given noise, the higher input amplitudes
have a higher SNDR if the gain is low. If higher gain is used for
input amplitudes in the range of 5mV − 10mV , the amplifier
output becomes nonlinear because the output swing goes out
of the linear range and hence degrades the SNDR of the AFE.
Hence a trade-off is required between power, noise, linearity
and the input impedance. The pseudo resistance also plays a
major role in contributing non-linearity. Thus for achieving a
high linearity, an output swing of 100mV is generally used [3].
In this paper two channels, one for high amplitude and other
for low amplitude signal conditioning are proposed shown in
Fig. 1 . The multiplexing is done through AGC. Signals above
1mV are digitized using a Σ∆ ADC and signals below 1mV
are digitized using SAR ADC. The AGC also controls the two
PGA’s as shown in Fig. 1. The IA and PGA are shared among
the two channels.
The rest of the paper is organized as follows. Section
II describes implementation of individual blocks Section III
describes the S/H, SAR and Σ∆ ADC. Section IV shows the
Fig. 2. Block diagram of instrumentation amplifier and programmable gain
amplifier. Here Cu = 0.5pF , M=10, Cg = 0.4pF and Cu1 = 0.4pF .
Fig. 3. Proposed improvised RFC amplifier for higher CMRR at lower
frequencies.
simulation results. Section V gives the conclusion.
II. IMPLEMENTATION OF INDIVIDUAL BLOCKS
A. Instrumentation Amplifier and Programmable Amplifier
The characteristics of an IA for biomedical signal acqui-
sition are as follows (1) A CMRR of greater than 70dB. (2)
An input impedance greater than 5MΩ at 50Hz (3) A high
pass filter for removing the baseline wandering. (4) A high
pass cutoff frequency lesser than 50mHz [8] (5) The low
pass cutoff is given by the UGB of the amplifier and the
closed loop gain. In this work, the gain of the IA is chosen
to be 10 to process a signal of 10mV as an output swing
of 100mV will give a high linearity. The Recycling Folded
cascode topology is used in IA [9]. This topology renders a
higher gain and gm compared to the folded cascode topology
for same power consumption. The differential gain for RFC is
given by (1) and respective common mode gain is given by (2).
The common mode gain of RFC with common mode feedback
is expressed as in (3). The use of lower gain in IA decreases
the CMRR as the differential gain is decreased. So to enhance
the CMRR, a gm cancellation technique is proposed on RFC
topology as shown in Fig. ??. The DC current flowing through
the transistors M3a/M4a is bypassed through M3c/M4c, which
decreases gm3. The expression for differential and common
mode gain for the proposed amplifier is given in (4) and (5)
respectively with CMFB.
AvDM = gm1a(K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9) (1)
AvCM =
gm1a(K − 1)
1 + gm0r0
∗ (gm5ro5(ro1a||ro3a)||gm7ro7ro9)
(2)
AvCM−CMFB =
gm1a(K − 1)
1 + gm0r0
∗ 1
gmcmfb
(3)
AV DM−proposed = gm1a(α∗K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9)
(4)
AV CM−CMFBproposed =
gm1a(α ∗K − 1)
1 + gm0r0
∗ 1
gmcmfb
(5)
The common mode reduction in bandwidth of IA can be
attributed to the introduction of a zero in the closed loop. The
location of the zero and poles for common mode feedback is
shown in (6).
H(s) =
sC1z2[1 +R1sC2 − gmcmfbR1]
[1 +R1(sC1 + sC2)][1 +
gmcmfbR1
R1sC2+1
+ sCLz2]
(6)
where the load capacitor is represented as CL and
z2 = R1||( 1
sC2
) (7)
Two PGA’s are used with a unity gain bandwidth higher
than lower cutoff frequency to avoid decrease in 3db bandwidth
with increase in gain. PGA’s gain is set by the capacitor ratios.
The PGA is implemented with RFC for K = 3 and α = 1.
The capacitor values are programmed by AGC for different
gains based on the input signal amplitude. The AGC consists
of a peak detector and a digital logic which calculates the peak
value and accordingly gain is set shown in Fig. 2.
1) Noise Analysis: The noise of the IA is contributed by
the modified RFC. The noise in RFC is generated by the flicker
noise from M3 and M9 transistors. The noise equation for the
RFC is shown in (8). In (8) µn and µp represents mobility
of NMOS and PMOS respectively. The noise of proposed
architecture is similar to RFC [9]. The major noise contribution
is by M1a, M1b, M3a, M3b and M9. The noise contributed by
M3b is higher compared to M3a in RFC because of current
multiplication. In proposed architecture the noise due to M3b
and M3a will reduce by α times but M3c contribution is
(1−α)∗K which adds up to same value. The noise contribution
due to M3c can be decreased by decreasing the gm3c and
decreasing the load current i.e. current through M9 and M10.
The noise of RFC and proposed architecture can be reduced
by choosing (1 < K < 3). The noise can also be reduced
by using source degeneration resistors for M3a and M3b. The
source degeneration resistors are neglected here to reduce the
area.
V 2f =
(
2 ∗Kp
CoxL1aW1a(1 +K) ∗ f
)
∗[
1 +K2
1 +K
+K∗KNµnCoxn
KPµpCoxp
(
L1a
L3a
)2(1+
W3a
W3b
)+
K − 1
K + 1
(
L1a
L9
)2
]
(8)
The total IA input referred noise power expression is shown in
(9). The first term is due to the pseudo resistor and the second
term is due to the capacitive feedback [6].
V 2in =
[[
1
sC1R1
]2
∗ V 2nres +
[
Cin + Cp + Cf
Cin
]2
∗ V 2f
]
(9)
B. Sample and Hold, Σ∆ ADC and SAR ADC
The signal from PGA is passed on to sample and hold
amplifier. There are two sample and hold in the proposed
system, one for SAR ADC operating at a sampling frequency
of 1 KHz, and the other for Σ∆ ADC operating at a sampling
frequency of 32 KHz [16]. For a signal swing of 100mV, the
10 bit SAR ADC achieves a 7 bit resolution. For signals of
amplitude greater than 2mVpp, a conventional discrete time
(DT) cascaded integrator feedback (CIFB) modulator with 2nd
order noise shaping is chosen with a reference voltage of
400mVpp Fig. 4. Owing to the fact that the integrator is the
most power hungry block of the SDM, twofold strategy was
employed to minimize the ADCs power consumption. The
integrator is implemented using the enhanced recyclic folded
cascode (ERFC) designed in 1V [10][11]. For DT Σ∆ ADC,
the use of transmission gates as switches require higher aspect
ratio for particular resistance which results in higher parasitic
capacitance. So to drive these switches, switch drivers are
required which consumes more power. The above constraint
can be avoided by using level shifted clock phases without
using transmission gates.
Fig. 4. Single ended representation of the fully differential opamp shared
DT Σ∆ ADC . The circuit renders 1st order noise shaping when only
components in black color are activated, and 2nd order noise shaping when the
components in dark red are also activated. Here CS1=0.67pF , CS2=2.02pF ,
CS fb=0.79pF , Ci1=4pF , and Vcm= 0.9V .
FOM1 =
Power(W ) ∗ 1012
2
SNR(dB)−1.76
6.02 ∗ 2 ∗BW (Hz)
pJ/Conv. (10)
III. RESULTS
The performance of proposed AFE is compared in Table
I. The linearity for lowest and highest values of input signal
to the system can be verified from THD in Table I. The
performance of Σ∆ ADC is compared in Table II. The FOM
is calculated by the expression (10), which explains the power
consumption per sample conversion. The common mode gain
is reduced by 20dB for 50Hz and 60Hz line can be verified
from Fig. 5. Frequency response of AFE with different gain
tuning is plotted in Fig. 6. An ECG signal of amplitude 1mV
is fed to the IA and the AGC performance was verified by
the output of the PGA as shown in Fig. 7. The resistance plot
Fig. 5. Comparison between common mode gains of the conventional and
the proposed amplifier.
Fig. 6. PGA gain reconfigurability.
of the pseudo resistor is given in Fig. 8. The FFT plot of the
output of the ADC for input of 20mVpp to AFE is plotted in
Fig. 9 for Σ∆ ADC and Fig. 10 for SAR ADC for an input
of 0.2mVpp.
IV. CONCLUSION
An ultra-Low power biomedical signal acquisition and
digitization is presented. The AFE does the work of filtering
and amplification with a linearity greater than 12bits. The AGC
controls the gain of the PGA such that the input to ADC is
100mV. Each block of AFE is designed for minimum power
using gm/ID methodology and hardware sharing and phase
level boosting is also implemented to minimize power con-
sumption of Σ∆ ADC. The required performance is achieved
with 1µW power..
(a) Input ECG signal (b) ECG output from AFE after fixing
appropriate gain through AGC.
Fig. 7. Input and output ECG plots.
Fig. 8. Resistance plot of pseudo resistor.
Fig. 9. Full system output power spectrum for a sinewave input of 20mVpp
processed by AFE, AGC, Sample and Hold and Σ∆ ADC, respectively.
Fig. 10. Full system output Spectrum for a sine wave input of 0.2mVpp
processed by AFE, AGC, Sample and Hold and SAR ADC.
TABLE I. PERFORMANCE OF THE PROPOSED AFE
Parameter Value
This work [5],2006 [14],2012 [15],2013
Technology (µm) 0.18 0.35 0.13 0.13
Voltage Supply (V) 1 1 1 1.5
Midband Gain (dB) 20-60 40.2 40 40
Bandwidth (Hz) 0.5-250 0.003-245 0.4-8.5K 19.9K
Input 6µVrms 2.7µVrms 3.2µVrms 3.7µVrms
Referred for for
Noise (0.05-250Hz) (0.05-250Hz)
NEF 3.32 - 4.5 3.04
Offset(3σ) 500 µV - - -
CMRR @50Hz (dB) 75 61-64 >60 >78
PSRR (dB) 77 62-63 >60 >80
0.057% 0.053% 1.5% 1%
@ 20mVpp @ 5mVpp @ 1mVpp 16.5mVpp
THD 0.067% @ 16Hz
@ 2mVpp
0.1%
@ 0.2mVpp
Current
Consumption (A) 300n 330n 12.5µ 2.6µ
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[1] Dessouky, M.; Kaiser, A., ”Very low-voltage digital-audio Σ∆ modulator
with 88-dB dynamic range using local switch bootstrapping,” Solid-State
TABLE II. PERFORMANCE OF THE Σ∆ ADC
Parameter Value
This work [12] [?]
Technology (µm) 0.18 0.18 0.18
Voltage Supply (V) 1 0.9 0.7
Order 2nd 2nd 2nd
Bandwidth (Hz) 500 10k 8k
Fs (MHz) 0.032 5 1.024
Power Consumption (µW ) 0.3 200 80
Dynamic Range (dB) 76 83 75
FOM1 (pJ/Conv.) 0.58 0.866 1.087
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[3] Xiaodan Zou; Xiaoyuan Xu; Libin Yao; Yong Lian, ”A 1-V 450-
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6-9 Feb. 2006
[6] Steyaert, M.S.J.; Sansen, W.M.C., ”A micropower low-noise monolithic
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General Enhancement of the Folded Cascode Amplifier,” Solid-State
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Research Archive of Indian Institute of Technology Hyderabad

See	discussions,	stats,	and	author	profiles	for	this	publication	at:	https://www.researchgate.net/publication/280878548A	True	1V	1	µW	Biomedical	Front	End	withReconfigurable	ADC	for	Self	powered	Smarter	IoTHealthcare	SystemsConference	Paper	·	July	2015CITATIONS0READS781	author:Pravanjan	PatraIndian	Institute	of	Technology	Hyderabad13	PUBLICATIONS			3	CITATIONS			SEE	PROFILEAll	in-text	references	underlined	in	blue	are	linked	to	publications	on	ResearchGate,letting	you	access	and	read	them	immediately.Available	from:	Pravanjan	PatraRetrieved	on:	01	September	2016A True 1V 1µW Biomedical Front End withReconfigurable ADC for Self powered Smarter IoTHealthcare SystemsPravanjan Patra, Kunal Yadav, Jairaj Naik, Ashudeb DuttaDepartment of Electrical Engineering, Indian Institute of Technology Hyderabad, India-502205Email: pravanjanpatra80@gmail.com;kunalyadav2@gmail.com; kr.jairaj.naik@gmail.com; asudeb dutta@iith.ac.inAbstract—This work proposes an ultralow power highly linearanalog front-end (AFE) with an input dynamic range from200µVpp to 20mVpp. The system consists of a signal condi-tioning instrumentation amplifier (IA), two programmable gainamplifiers (PGA), a mixed signal automatic gain control (AGC),two sample and hold (S/H), a 10 bit successive approximationregister (SAR) analog to digital converter (ADC), and a Σ∆modulator with 10 bit effective number of bits (ENOB). Ahighly linear capacitively-coupled IA is achieved by increasing itsfeedback factor. Moreover, a transconductance (gm) cancellationtechnique is proposed for achieving a high common moderejection ratio (CMRR). The conditioned signal is digitized usinga SAR ADC for an input range of 200µVpp to 2mVpp, and,an opamp-shared Σ∆ ADC for an input range of 2mVpp to20mVpp. The selection between the two ADCs is done by theAGC. The full system is designed using 1V supply in UMC0.18µm CMOS technology. The AFE (IA and the two PGAs)achieves an overall linearity of more than 12 bits, for an inputrange of 200µVpp to 20mVpp while consuming 300nW witha bandwidth of 0.05− 250Hz. The power consumption of theSAR ADC is 40nW while operating at a sampling frequencyof 1KHz. The Σ∆ ADC consumes 300nW at a samplingfrequency of 32KHz with an OSR of 32. The proposed systemis intended to be powered by an energy scavenging circuit withoutcompromising its own performance. The system was successfullytested for an ECG signal obtained from PTB database.I. INTRODUCTIONThe growing demand for a low power, miniature bio-potential signal acquisition and digitization system is themotivation for this work. Recent research shows that majorityof cardiac diseases are caused due to unhealthy habits e.g.improper diet, meager exercise, etc. A patient-centric health-care system, emphasizing on prevention of such diseases andcontinuous monitoring, becomes most relevant in the presentscenario. For such a healthcare system a portable, light weightand microscopic devices are in demand. The major bottleneckin the design of these systems is it’s power consumption.The power of the system can be scaled by using a highertransconductance efficiency (gm/ID) of input devices andlower supply voltage for a particular technology node. Butthe supply voltage cannot be scaled below Vthn + Vthp asswitches will not be able to operate [1]. Further utilizing ahigher gm/ID of input transistor will result in lower linearityin high gain stages. So a proper optimized value of gm/IDis required for obtaining higher gain, linearity, output swing,while rendering low noise and consuming less power [2].The bio-potential signal amplitude varies from tens of µVFig. 1. Block diagram of the proposed acquisition system.to tens of mV [3][4]. So acquisition system should have anoise level below the minimum signal amplitude for faithfuldigitization by the subsequent ADCs. The noise of the systemis majorly contributed by the IA. Moreover, the flicker noiseof IA dominates the overall noise, which in turn degradesthe signal to noise plus distortion ratio (SNDR) of the wholesystem. The flicker noise can be decreased by increasing thewidth (W) of input transistors (gm) [5] for a particular biascurrent, which results in increase of parasitic capacitance.The increase in the input referred noise in gain stages withcapacitive feedback is inversely proportional to the net inputcapacitance [6]. To reduce the input referred noise a highinput capacitor has to be used which leads to a lower inputimpedance. The input capacitor should be less than 100pF tohave an impedance higher than 5MΩ at 50Hz for power linerejection [7]. For a given noise, the higher input amplitudeshave a higher SNDR if the gain is low. If higher gain is used forinput amplitudes in the range of 5mV − 10mV , the amplifieroutput becomes nonlinear because the output swing goes outof the linear range and hence degrades the SNDR of the AFE.Hence a trade-off is required between power, noise, linearityand the input impedance. The pseudo resistance also plays amajor role in contributing non-linearity. Thus for achieving ahigh linearity, an output swing of 100mV is generally used [3].In this paper two channels, one for high amplitude and otherfor low amplitude signal conditioning are proposed shown inFig. 1 . The multiplexing is done through AGC. Signals above1mV are digitized using a Σ∆ ADC and signals below 1mVare digitized using SAR ADC. The AGC also controls the twoPGA’s as shown in Fig. 1. The IA and PGA are shared amongthe two channels.The rest of the paper is organized as follows. SectionII describes implementation of individual blocks Section IIIdescribes the S/H, SAR and Σ∆ ADC. Section IV shows theFig. 2. Block diagram of instrumentation amplifier and programmable gainamplifier. Here Cu = 0.5pF , M=10, Cg = 0.4pF and Cu1 = 0.4pF .Fig. 3. Proposed improvised RFC amplifier for higher CMRR at lowerfrequencies.simulation results. Section V gives the conclusion.II. IMPLEMENTATION OF INDIVIDUAL BLOCKSA. Instrumentation Amplifier and Programmable AmplifierThe characteristics of an IA for biomedical signal acqui-sition are as follows (1) A CMRR of greater than 70dB. (2)An input impedance greater than 5MΩ at 50Hz (3) A highpass filter for removing the baseline wandering. (4) A highpass cutoff frequency lesser than 50mHz [8] (5) The lowpass cutoff is given by the UGB of the amplifier and theclosed loop gain. In this work, the gain of the IA is chosento be 10 to process a signal of 10mV as an output swingof 100mV will give a high linearity. The Recycling Foldedcascode topology is used in IA [9]. This topology renders ahigher gain and gm compared to the folded cascode topologyfor same power consumption. The differential gain for RFC isgiven by (1) and respective common mode gain is given by (2).The common mode gain of RFC with common mode feedbackis expressed as in (3). The use of lower gain in IA decreasesthe CMRR as the differential gain is decreased. So to enhancethe CMRR, a gm cancellation technique is proposed on RFCtopology as shown in Fig. ??. The DC current flowing throughthe transistors M3a/M4a is bypassed through M3c/M4c, whichdecreases gm3. The expression for differential and commonmode gain for the proposed amplifier is given in (4) and (5)respectively with CMFB.AvDM = gm1a(K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9) (1)AvCM =gm1a(K − 1)1 + gm0r0∗ (gm5ro5(ro1a||ro3a)||gm7ro7ro9)(2)AvCM−CMFB =gm1a(K − 1)1 + gm0r0∗ 1gmcmfb(3)AV DM−proposed = gm1a(α∗K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9)(4)AV CM−CMFBproposed =gm1a(α ∗K − 1)1 + gm0r0∗ 1gmcmfb(5)The common mode reduction in bandwidth of IA can beattributed to the introduction of a zero in the closed loop. Thelocation of the zero and poles for common mode feedback isshown in (6).H(s) =sC1z2[1 +R1sC2 − gmcmfbR1][1 +R1(sC1 + sC2)][1 +gmcmfbR1R1sC2+1+ sCLz2](6)where the load capacitor is represented as CL andz2 = R1||( 1sC2) (7)Two PGA’s are used with a unity gain bandwidth higherthan lower cutoff frequency to avoid decrease in 3db bandwidthwith increase in gain. PGA’s gain is set by the capacitor ratios.The PGA is implemented with RFC for K = 3 and α = 1.The capacitor values are programmed by AGC for differentgains based on the input signal amplitude. The AGC consistsof a peak detector and a digital logic which calculates the peakvalue and accordingly gain is set shown in Fig. 2.1) Noise Analysis: The noise of the IA is contributed bythe modified RFC. The noise in RFC is generated by the flickernoise from M3 and M9 transistors. The noise equation for theRFC is shown in (8). In (8) µn and µp represents mobilityof NMOS and PMOS respectively. The noise of proposedarchitecture is similar to RFC [9]. The major noise contributionis by M1a, M1b, M3a, M3b and M9. The noise contributed byM3b is higher compared to M3a in RFC because of currentmultiplication. In proposed architecture the noise due to M3band M3a will reduce by α times but M3c contribution is(1−α)∗K which adds up to same value. The noise contributiondue to M3c can be decreased by decreasing the gm3c anddecreasing the load current i.e. current through M9 and M10.The noise of RFC and proposed architecture can be reducedby choosing (1 < K < 3). The noise can also be reducedby using source degeneration resistors for M3a and M3b. Thesource degeneration resistors are neglected here to reduce thearea.V 2f =(2 ∗KpCoxL1aW1a(1 +K) ∗ f)∗[1 +K21 +K+K∗KNµnCoxnKPµpCoxp(L1aL3a)2(1+W3aW3b)+K − 1K + 1(L1aL9)2](8)The total IA input referred noise power expression is shown in(9). The first term is due to the pseudo resistor and the secondterm is due to the capacitive feedback [6].V 2in =[[1sC1R1]2∗ V 2nres +[Cin + Cp + CfCin]2∗ V 2f](9)B. Sample and Hold, Σ∆ ADC and SAR ADCThe signal from PGA is passed on to sample and holdamplifier. There are two sample and hold in the proposedsystem, one for SAR ADC operating at a sampling frequencyof 1 KHz, and the other for Σ∆ ADC operating at a samplingfrequency of 32 KHz [16]. For a signal swing of 100mV, the10 bit SAR ADC achieves a 7 bit resolution. For signals ofamplitude greater than 2mVpp, a conventional discrete time(DT) cascaded integrator feedback (CIFB) modulator with 2ndorder noise shaping is chosen with a reference voltage of400mVpp Fig. 4. Owing to the fact that the integrator is themost power hungry block of the SDM, twofold strategy wasemployed to minimize the ADCs power consumption. Theintegrator is implemented using the enhanced recyclic foldedcascode (ERFC) designed in 1V [10][11]. For DT Σ∆ ADC,the use of transmission gates as switches require higher aspectratio for particular resistance which results in higher parasiticcapacitance. So to drive these switches, switch drivers arerequired which consumes more power. The above constraintcan be avoided by using level shifted clock phases withoutusing transmission gates.Fig. 4. Single ended representation of the fully differential opamp sharedDT Σ∆ ADC . The circuit renders 1st order noise shaping when onlycomponents in black color are activated, and 2nd order noise shaping when thecomponents in dark red are also activated. Here CS1=0.67pF , CS2=2.02pF ,CS fb=0.79pF , Ci1=4pF , and Vcm= 0.9V .FOM1 =Power(W ) ∗ 10122SNR(dB)−1.766.02 ∗ 2 ∗BW (Hz)pJ/Conv. (10)III. RESULTSThe performance of proposed AFE is compared in TableI. The linearity for lowest and highest values of input signalto the system can be verified from THD in Table I. Theperformance of Σ∆ ADC is compared in Table II. The FOMis calculated by the expression (10), which explains the powerconsumption per sample conversion. The common mode gainis reduced by 20dB for 50Hz and 60Hz line can be verifiedfrom Fig. 5. Frequency response of AFE with different gaintuning is plotted in Fig. 6. An ECG signal of amplitude 1mVis fed to the IA and the AGC performance was verified bythe output of the PGA as shown in Fig. 7. The resistance plotFig. 5. Comparison between common mode gains of the conventional andthe proposed amplifier.Fig. 6. PGA gain reconfigurability.of the pseudo resistor is given in Fig. 8. The FFT plot of theoutput of the ADC for input of 20mVpp to AFE is plotted inFig. 9 for Σ∆ ADC and Fig. 10 for SAR ADC for an inputof 0.2mVpp.IV. CONCLUSIONAn ultra-Low power biomedical signal acquisition anddigitization is presented. The AFE does the work of filteringand amplification with a linearity greater than 12bits. The AGCcontrols the gain of the PGA such that the input to ADC is100mV. Each block of AFE is designed for minimum powerusing gm/ID methodology and hardware sharing and phaselevel boosting is also implemented to minimize power con-sumption of Σ∆ ADC. The required performance is achievedwith 1µW power..(a) Input ECG signal (b) ECG output from AFE after fixingappropriate gain through AGC.Fig. 7. Input and output ECG plots.Fig. 8. Resistance plot of pseudo resistor.Fig. 9. Full system output power spectrum for a sinewave input of 20mVppprocessed by AFE, AGC, Sample and Hold and Σ∆ ADC, respectively.Fig. 10. Full system output Spectrum for a sine wave input of 0.2mVppprocessed by AFE, AGC, Sample and Hold and SAR ADC.TABLE I. PERFORMANCE OF THE PROPOSED AFEParameter ValueThis work [5],2006 [14],2012 [15],2013Technology (µm) 0.18 0.35 0.13 0.13Voltage Supply (V) 1 1 1 1.5Midband Gain (dB) 20-60 40.2 40 40Bandwidth (Hz) 0.5-250 0.003-245 0.4-8.5K 19.9KInput 6µVrms 2.7µVrms 3.2µVrms 3.7µVrmsReferred for forNoise (0.05-250Hz) (0.05-250Hz)NEF 3.32 - 4.5 3.04Offset(3σ) 500 µV - - -CMRR @50Hz (dB) 75 61-64 >60 >78PSRR (dB) 77 62-63 >60 >800.057% 0.053% 1.5% 1%@ 20mVpp @ 5mVpp @ 1mVpp 16.5mVppTHD 0.067% @ 16Hz@ 2mVpp0.1%@ 0.2mVppCurrentConsumption (A) 300n 330n 12.5µ 2.6µREFERENCES[1] Dessouky, M.; Kaiser, A., ”Very low-voltage digital-audio Σ∆ modulatorwith 88-dB dynamic range using local switch bootstrapping,” Solid-StateTABLE II. PERFORMANCE OF THE Σ∆ ADCParameter ValueThis work [12] [?]Technology (µm) 0.18 0.18 0.18Voltage Supply (V) 1 0.9 0.7Order 2nd 2nd 2ndBandwidth (Hz) 500 10k 8kFs (MHz) 0.032 5 1.024Power Consumption (µW ) 0.3 200 80Dynamic Range (dB) 76 83 75FOM1 (pJ/Conv.) 0.58 0.866 1.087Circuits, IEEE Journal of , vol.36, no.3, pp.349,355, Mar 2001.[2] Wattanapanitch, W.; Fee, M.; Sarpeshkar, R., ”An Energy-EfficientMicropower Neural Recording Amplifier,” Biomedical Circuits and Sys-tems, IEEE Transactions on , vol.1, no.2, pp.136,147, June 2007.[3] Xiaodan Zou; Xiaoyuan Xu; Libin Yao; Yong Lian, ”A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,”Solid-State Circuits, IEEE Journal of , vol.44, no.4, pp.1067,1077, April2009.[4] Qinwen Fan; Sebastiano, F.; Huijsing, J.H.; Makinwa, K.A.A., ”A 1.8W60 nV/sqrt Hz Capacitively-Coupled Chopper Instrumentation Amplifierin 65 nm CMOS for Wireless Sensor Nodes,” Solid-State Circuits, IEEEJournal of , vol.46, no.7, pp.1534,1543, July 2011.[5] Honglei Wu; Yong Ping Xu, ”A 1V 2.3/spl mu/W Biomedical SignalAcquisition IC,” Solid-State Circuits Conference, 2006. ISSCC 2006.Digest of Technical Papers. IEEE International , vol., no., pp.119,128,6-9 Feb. 2006[6] Steyaert, M.S.J.; Sansen, W.M.C., ”A micropower low-noise monolithicinstrumentation amplifier for medical purposes,” Solid-State Circuits,IEEE Journal of , vol.22, no.6, pp.1163,1168, Dec 1987.[7] Pallas-Areny, R., ”Interference-rejection characteristics of biopotentialamplifiers: a comparative analysis,” Biomedical Engineering, IEEETransactions on , vol.35, no.11, pp.953,959, Nov. 1988.[8] Shuenn-Yuh Lee, Jia-Hua Hong, Jin-Ching Lee and Qiang Fang (2012).An Analogue-Front System with a Low-Power On-Chip Filter and ADCfor portable ECG Detection Devices, Advances in Electrocardiograms-Methods and Analysis, PhD. Richard Millis.[9] Assaad, R.S.; Silva-Martinez, J., ”The Recycling Folded Cascode: AGeneral Enhancement of the Folded Cascode Amplifier,” Solid-StateCircuits, IEEE Journal of , vol.44, no.9, pp.2535,2542, Sept. 2009[10] Patra, P.; Kumaravel, S.; Venkatramani, B., ”An enhanced fully dif-ferential Recyclic Folded Cascode OTA,” Systems, Signals and Devices(SSD), 2012 9th International Multi-Conference on , vol., no., pp.1,5,20-23 March 2012.[11] Patra, P.; Jha, P.K.; Dutta, A., ”An enhanced recycling folded cas-cade OTA with a positive feedback,” Microelectronics and Electronics(PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Re-search in , vol., no., pp.153,157, 19-21 Dec. 2013.[12] Goes, J.; Vaz, B.; Monteiro, R.; Paulino, N., ”A 0.9V /spl Delta//splSigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-PhaseTechnique,” Solid-State Circuits Conference, 2006. ISSCC 2006. Digestof Technical Papers. IEEE International , vol., no., pp.191,200, 6-9 Feb.2006.[13] Sauerbrey, J.; Tille, T.; Schmitt-Landsiedel, D.; Thewes, R., ”A 0.7VMOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator,” Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC.2002 IEEE International , vol.1, no., pp.310,469 vol.1, 7-7 Feb. 2002.[14] Fan Zhang; Holleman, J.; Otis, B.P., ”Design of Ultra-LowPower Biopotential Amplifiers for Biosignal Acquisition Applications,”Biomedical Circuits and Systems, IEEE Transactions on , vol.6, no.4,pp.344,355, Aug. 2012.[15] M. Young, The Technical Writer’s Handbook. Mill Valley, CA: Uni-versity Science, 198 Johnson, B.; Molnar, A., ”An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing,” Solid-State Circuits, IEEEJournal of , vol.48, no.6, pp.1487,1496, June 2013.[16] Dai Zhang; Bhide, A.; Alvandpour, A., ”A 53-nW 9.1-ENOB 1-kS/sSAR ADC in 0.13µm CMOS for Medical Implant Devices,” Solid-StateCircuits, IEEE Journal of , vol.47, no.7, pp.1585,1593, July 2012

Pravanjan Patra

Kunal Yadav

Jairaj Naik

Ashudeb Dutta

Crossref

See	discussions,	stats,	and	author	profiles	for	this	publication	at:	https://www.researchgate.net/publication/280878548A	True	1V	1	µW	Biomedical	Front	End	withReconfigurable	ADC	for	Self	powered	Smarter	IoTHealthcare	SystemsConference	Paper	·	July	2015READS501	author:Pravanjan	PatraIndian	Institute	of	Technology	Hyderabad13	PUBLICATIONS			3	CITATIONS			SEE	PROFILEAll	in-text	references	underlined	in	blue	are	linked	to	publications	on	ResearchGate,letting	you	access	and	read	them	immediately.Available	from:	Pravanjan	PatraRetrieved	on:	21	April	2016A True 1V 1µW Biomedical Front End withReconfigurable ADC for Self powered Smarter IoTHealthcare SystemsPravanjan Patra, Kunal Yadav, Jairaj Naik, Ashudeb DuttaDepartment of Electrical Engineering, Indian Institute of Technology Hyderabad, India-502205Email: pravanjanpatra80@gmail.com;kunalyadav2@gmail.com; kr.jairaj.naik@gmail.com; asudeb dutta@iith.ac.inAbstract—This work proposes an ultralow power highly linearanalog front-end (AFE) with an input dynamic range from200µVpp to 20mVpp. The system consists of a signal condi-tioning instrumentation amplifier (IA), two programmable gainamplifiers (PGA), a mixed signal automatic gain control (AGC),two sample and hold (S/H), a 10 bit successive approximationregister (SAR) analog to digital converter (ADC), and a Σ∆modulator with 10 bit effective number of bits (ENOB). Ahighly linear capacitively-coupled IA is achieved by increasing itsfeedback factor. Moreover, a transconductance (gm) cancellationtechnique is proposed for achieving a high common moderejection ratio (CMRR). The conditioned signal is digitized usinga SAR ADC for an input range of 200µVpp to 2mVpp, and,an opamp-shared Σ∆ ADC for an input range of 2mVpp to20mVpp. The selection between the two ADCs is done by theAGC. The full system is designed using 1V supply in UMC0.18µm CMOS technology. The AFE (IA and the two PGAs)achieves an overall linearity of more than 12 bits, for an inputrange of 200µVpp to 20mVpp while consuming 300nW witha bandwidth of 0.05− 250Hz. The power consumption of theSAR ADC is 40nW while operating at a sampling frequencyof 1KHz. The Σ∆ ADC consumes 300nW at a samplingfrequency of 32KHz with an OSR of 32. The proposed systemis intended to be powered by an energy scavenging circuit withoutcompromising its own performance. The system was successfullytested for an ECG signal obtained from PTB database.I. INTRODUCTIONThe growing demand for a low power, miniature bio-potential signal acquisition and digitization system is themotivation for this work. Recent research shows that majorityof cardiac diseases are caused due to unhealthy habits e.g.improper diet, meager exercise, etc. A patient-centric health-care system, emphasizing on prevention of such diseases andcontinuous monitoring, becomes most relevant in the presentscenario. For such a healthcare system a portable, light weightand microscopic devices are in demand. The major bottleneckin the design of these systems is it’s power consumption.The power of the system can be scaled by using a highertransconductance efficiency (gm/ID) of input devices andlower supply voltage for a particular technology node. Butthe supply voltage cannot be scaled below Vthn + Vthp asswitches will not be able to operate [1]. Further utilizing ahigher gm/ID of input transistor will result in lower linearityin high gain stages. So a proper optimized value of gm/IDis required for obtaining higher gain, linearity, output swing,while rendering low noise and consuming less power [2].The bio-potential signal amplitude varies from tens of µVFig. 1. Block diagram of the proposed acquisition system.to tens of mV [3][4]. So acquisition system should have anoise level below the minimum signal amplitude for faithfuldigitization by the subsequent ADCs. The noise of the systemis majorly contributed by the IA. Moreover, the flicker noiseof IA dominates the overall noise, which in turn degradesthe signal to noise plus distortion ratio (SNDR) of the wholesystem. The flicker noise can be decreased by increasing thewidth (W) of input transistors (gm) [5] for a particular biascurrent, which results in increase of parasitic capacitance.The increase in the input referred noise in gain stages withcapacitive feedback is inversely proportional to the net inputcapacitance [6]. To reduce the input referred noise a highinput capacitor has to be used which leads to a lower inputimpedance. The input capacitor should be less than 100pF tohave an impedance higher than 5MΩ at 50Hz for power linerejection [7]. For a given noise, the higher input amplitudeshave a higher SNDR if the gain is low. If higher gain is used forinput amplitudes in the range of 5mV − 10mV , the amplifieroutput becomes nonlinear because the output swing goes outof the linear range and hence degrades the SNDR of the AFE.Hence a trade-off is required between power, noise, linearityand the input impedance. The pseudo resistance also plays amajor role in contributing non-linearity. Thus for achieving ahigh linearity, an output swing of 100mV is generally used [3].In this paper two channels, one for high amplitude and otherfor low amplitude signal conditioning are proposed shown inFig. 1 . The multiplexing is done through AGC. Signals above1mV are digitized using a Σ∆ ADC and signals below 1mVare digitized using SAR ADC. The AGC also controls the twoPGA’s as shown in Fig. 1. The IA and PGA are shared amongthe two channels.The rest of the paper is organized as follows. SectionII describes implementation of individual blocks Section IIIdescribes the S/H, SAR and Σ∆ ADC. Section IV shows theFig. 2. Block diagram of instrumentation amplifier and programmable gainamplifier. Here Cu = 0.5pF , M=10, Cg = 0.4pF and Cu1 = 0.4pF .Fig. 3. Proposed improvised RFC amplifier for higher CMRR at lowerfrequencies.simulation results. Section V gives the conclusion.II. IMPLEMENTATION OF INDIVIDUAL BLOCKSA. Instrumentation Amplifier and Programmable AmplifierThe characteristics of an IA for biomedical signal acqui-sition are as follows (1) A CMRR of greater than 70dB. (2)An input impedance greater than 5MΩ at 50Hz (3) A highpass filter for removing the baseline wandering. (4) A highpass cutoff frequency lesser than 50mHz [8] (5) The lowpass cutoff is given by the UGB of the amplifier and theclosed loop gain. In this work, the gain of the IA is chosento be 10 to process a signal of 10mV as an output swingof 100mV will give a high linearity. The Recycling Foldedcascode topology is used in IA [9]. This topology renders ahigher gain and gm compared to the folded cascode topologyfor same power consumption. The differential gain for RFC isgiven by (1) and respective common mode gain is given by (2).The common mode gain of RFC with common mode feedbackis expressed as in (3). The use of lower gain in IA decreasesthe CMRR as the differential gain is decreased. So to enhancethe CMRR, a gm cancellation technique is proposed on RFCtopology as shown in Fig. ??. The DC current flowing throughthe transistors M3a/M4a is bypassed through M3c/M4c, whichdecreases gm3. The expression for differential and commonmode gain for the proposed amplifier is given in (4) and (5)respectively with CMFB.AvDM = gm1a(K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9) (1)AvCM =gm1a(K − 1)1 + gm0r0∗ (gm5ro5(ro1a||ro3a)||gm7ro7ro9)(2)AvCM−CMFB =gm1a(K − 1)1 + gm0r0∗ 1gmcmfb(3)AV DM−proposed = gm1a(α∗K+1)∗(gm5ro5(ro1a||ro3a)||gm7ro7ro9)(4)AV CM−CMFBproposed =gm1a(α ∗K − 1)1 + gm0r0∗ 1gmcmfb(5)The common mode reduction in bandwidth of IA can beattributed to the introduction of a zero in the closed loop. Thelocation of the zero and poles for common mode feedback isshown in (6).H(s) =sC1z2[1 +R1sC2 − gmcmfbR1][1 +R1(sC1 + sC2)][1 +gmcmfbR1R1sC2+1+ sCLz2](6)where the load capacitor is represented as CL andz2 = R1||( 1sC2) (7)Two PGA’s are used with a unity gain bandwidth higherthan lower cutoff frequency to avoid decrease in 3db bandwidthwith increase in gain. PGA’s gain is set by the capacitor ratios.The PGA is implemented with RFC for K = 3 and α = 1.The capacitor values are programmed by AGC for differentgains based on the input signal amplitude. The AGC consistsof a peak detector and a digital logic which calculates the peakvalue and accordingly gain is set shown in Fig. 2.1) Noise Analysis: The noise of the IA is contributed bythe modified RFC. The noise in RFC is generated by the flickernoise from M3 and M9 transistors. The noise equation for theRFC is shown in (8). In (8) µn and µp represents mobilityof NMOS and PMOS respectively. The noise of proposedarchitecture is similar to RFC [9]. The major noise contributionis by M1a, M1b, M3a, M3b and M9. The noise contributed byM3b is higher compared to M3a in RFC because of currentmultiplication. In proposed architecture the noise due to M3band M3a will reduce by α times but M3c contribution is(1−α)∗K which adds up to same value. The noise contributiondue to M3c can be decreased by decreasing the gm3c anddecreasing the load current i.e. current through M9 and M10.The noise of RFC and proposed architecture can be reducedby choosing (1 < K < 3). The noise can also be reducedby using source degeneration resistors for M3a and M3b. Thesource degeneration resistors are neglected here to reduce thearea.V 2f =(2 ∗KpCoxL1aW1a(1 +K) ∗ f)∗[1 +K21 +K+K∗KNµnCoxnKPµpCoxp(L1aL3a)2(1+W3aW3b)+K − 1K + 1(L1aL9)2](8)The total IA input referred noise power expression is shown in(9). The first term is due to the pseudo resistor and the secondterm is due to the capacitive feedback [6].V 2in =[[1sC1R1]2∗ V 2nres +[Cin + Cp + CfCin]2∗ V 2f](9)B. Sample and Hold, Σ∆ ADC and SAR ADCThe signal from PGA is passed on to sample and holdamplifier. There are two sample and hold in the proposedsystem, one for SAR ADC operating at a sampling frequencyof 1 KHz, and the other for Σ∆ ADC operating at a samplingfrequency of 32 KHz [16]. For a signal swing of 100mV, the10 bit SAR ADC achieves a 7 bit resolution. For signals ofamplitude greater than 2mVpp, a conventional discrete time(DT) cascaded integrator feedback (CIFB) modulator with 2ndorder noise shaping is chosen with a reference voltage of400mVpp Fig. 4. Owing to the fact that the integrator is themost power hungry block of the SDM, twofold strategy wasemployed to minimize the ADCs power consumption. Theintegrator is implemented using the enhanced recyclic foldedcascode (ERFC) designed in 1V [10][11]. For DT Σ∆ ADC,the use of transmission gates as switches require higher aspectratio for particular resistance which results in higher parasiticcapacitance. So to drive these switches, switch drivers arerequired which consumes more power. The above constraintcan be avoided by using level shifted clock phases withoutusing transmission gates.Fig. 4. Single ended representation of the fully differential opamp sharedDT Σ∆ ADC . The circuit renders 1st order noise shaping when onlycomponents in black color are activated, and 2nd order noise shaping when thecomponents in dark red are also activated. Here CS1=0.67pF , CS2=2.02pF ,CS fb=0.79pF , Ci1=4pF , and Vcm= 0.9V .FOM1 =Power(W ) ∗ 10122SNR(dB)−1.766.02 ∗ 2 ∗BW (Hz)pJ/Conv. (10)III. RESULTSThe performance of proposed AFE is compared in TableI. The linearity for lowest and highest values of input signalto the system can be verified from THD in Table I. Theperformance of Σ∆ ADC is compared in Table II. The FOMis calculated by the expression (10), which explains the powerconsumption per sample conversion. The common mode gainis reduced by 20dB for 50Hz and 60Hz line can be verifiedfrom Fig. 5. Frequency response of AFE with different gaintuning is plotted in Fig. 6. An ECG signal of amplitude 1mVis fed to the IA and the AGC performance was verified bythe output of the PGA as shown in Fig. 7. The resistance plotFig. 5. Comparison between common mode gains of the conventional andthe proposed amplifier.Fig. 6. PGA gain reconfigurability.of the pseudo resistor is given in Fig. 8. The FFT plot of theoutput of the ADC for input of 20mVpp to AFE is plotted inFig. 9 for Σ∆ ADC and Fig. 10 for SAR ADC for an inputof 0.2mVpp.IV. CONCLUSIONAn ultra-Low power biomedical signal acquisition anddigitization is presented. The AFE does the work of filteringand amplification with a linearity greater than 12bits. The AGCcontrols the gain of the PGA such that the input to ADC is100mV. Each block of AFE is designed for minimum powerusing gm/ID methodology and hardware sharing and phaselevel boosting is also implemented to minimize power con-sumption of Σ∆ ADC. The required performance is achievedwith 1µW power..(a) Input ECG signal (b) ECG output from AFE after fixingappropriate gain through AGC.Fig. 7. Input and output ECG plots.Fig. 8. Resistance plot of pseudo resistor.Fig. 9. Full system output power spectrum for a sinewave input of 20mVppprocessed by AFE, AGC, Sample and Hold and Σ∆ ADC, respectively.Fig. 10. Full system output Spectrum for a sine wave input of 0.2mVppprocessed by AFE, AGC, Sample and Hold and SAR ADC.TABLE I. PERFORMANCE OF THE PROPOSED AFEParameter ValueThis work [5],2006 [14],2012 [15],2013Technology (µm) 0.18 0.35 0.13 0.13Voltage Supply (V) 1 1 1 1.5Midband Gain (dB) 20-60 40.2 40 40Bandwidth (Hz) 0.5-250 0.003-245 0.4-8.5K 19.9KInput 6µVrms 2.7µVrms 3.2µVrms 3.7µVrmsReferred for forNoise (0.05-250Hz) (0.05-250Hz)NEF 3.32 - 4.5 3.04Offset(3σ) 500 µV - - -CMRR @50Hz (dB) 75 61-64 >60 >78PSRR (dB) 77 62-63 >60 >800.057% 0.053% 1.5% 1%@ 20mVpp @ 5mVpp @ 1mVpp 16.5mVppTHD 0.067% @ 16Hz@ 2mVpp0.1%@ 0.2mVppCurrentConsumption (A) 300n 330n 12.5µ 2.6µREFERENCES[1] Dessouky, M.; Kaiser, A., ”Very low-voltage digital-audio Σ∆ modulatorwith 88-dB dynamic range using local switch bootstrapping,” Solid-StateTABLE II. PERFORMANCE OF THE Σ∆ ADCParameter ValueThis work [12] [?]Technology (µm) 0.18 0.18 0.18Voltage Supply (V) 1 0.9 0.7Order 2nd 2nd 2ndBandwidth (Hz) 500 10k 8kFs (MHz) 0.032 5 1.024Power Consumption (µW ) 0.3 200 80Dynamic Range (dB) 76 83 75FOM1 (pJ/Conv.) 0.58 0.866 1.087Circuits, IEEE Journal of , vol.36, no.3, pp.349,355, Mar 2001.[2] Wattanapanitch, W.; Fee, M.; Sarpeshkar, R., ”An Energy-EfficientMicropower Neural Recording Amplifier,” Biomedical Circuits and Sys-tems, IEEE Transactions on , vol.1, no.2, pp.136,147, June 2007.[3] Xiaodan Zou; Xiaoyuan Xu; Libin Yao; Yong Lian, ”A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,”Solid-State Circuits, IEEE Journal of , vol.44, no.4, pp.1067,1077, April2009.[4] Qinwen Fan; Sebastiano, F.; Huijsing, J.H.; Makinwa, K.A.A., ”A 1.8W60 nV/sqrt Hz Capacitively-Coupled Chopper Instrumentation Amplifierin 65 nm CMOS for Wireless Sensor Nodes,” Solid-State Circuits, IEEEJournal of , vol.46, no.7, pp.1534,1543, July 2011.[5] Honglei Wu; Yong Ping Xu, ”A 1V 2.3/spl mu/W Biomedical SignalAcquisition IC,” Solid-State Circuits Conference, 2006. ISSCC 2006.Digest of Technical Papers. IEEE International , vol., no., pp.119,128,6-9 Feb. 2006[6] Steyaert, M.S.J.; Sansen, W.M.C., ”A micropower low-noise monolithicinstrumentation amplifier for medical purposes,” Solid-State Circuits,IEEE Journal of , vol.22, no.6, pp.1163,1168, Dec 1987.[7] Pallas-Areny, R., ”Interference-rejection characteristics of biopotentialamplifiers: a comparative analysis,” Biomedical Engineering, IEEETransactions on , vol.35, no.11, pp.953,959, Nov. 1988.[8] Shuenn-Yuh Lee, Jia-Hua Hong, Jin-Ching Lee and Qiang Fang (2012).An Analogue-Front System with a Low-Power On-Chip Filter and ADCfor portable ECG Detection Devices, Advances in Electrocardiograms-Methods and Analysis, PhD. Richard Millis.[9] Assaad, R.S.; Silva-Martinez, J., ”The Recycling Folded Cascode: AGeneral Enhancement of the Folded Cascode Amplifier,” Solid-StateCircuits, IEEE Journal of , vol.44, no.9, pp.2535,2542, Sept. 2009[10] Patra, P.; Kumaravel, S.; Venkatramani, B., ”An enhanced fully dif-ferential Recyclic Folded Cascode OTA,” Systems, Signals and Devices(SSD), 2012 9th International Multi-Conference on , vol., no., pp.1,5,20-23 March 2012.[11] Patra, P.; Jha, P.K.; Dutta, A., ”An enhanced recycling folded cas-cade OTA with a positive feedback,” Microelectronics and Electronics(PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Re-search in , vol., no., pp.153,157, 19-21 Dec. 2013.[12] Goes, J.; Vaz, B.; Monteiro, R.; Paulino, N., ”A 0.9V /spl Delta//splSigma/ Modulator with 80dB SNDR and 83dB DR Using a Single-PhaseTechnique,” Solid-State Circuits Conference, 2006. ISSCC 2006. Digestof Technical Papers. IEEE International , vol., no., pp.191,200, 6-9 Feb.2006.[13] Sauerbrey, J.; Tille, T.; Schmitt-Landsiedel, D.; Thewes, R., ”A 0.7VMOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator,” Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC.2002 IEEE International , vol.1, no., pp.310,469 vol.1, 7-7 Feb. 2002.[14] Fan Zhang; Holleman, J.; Otis, B.P., ”Design of Ultra-LowPower Biopotential Amplifiers for Biosignal Acquisition Applications,”Biomedical Circuits and Systems, IEEE Transactions on , vol.6, no.4,pp.344,355, Aug. 2012.[15] M. Young, The Technical Writer’s Handbook. Mill Valley, CA: Uni-versity Science, 198 Johnson, B.; Molnar, A., ”An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing,” Solid-State Circuits, IEEEJournal of , vol.48, no.6, pp.1487,1496, June 2013.[16] Dai Zhang; Bhide, A.; Alvandpour, A., ”A 53-nW 9.1-ENOB 1-kS/sSAR ADC in 0.13µm CMOS for Medical Implant Devices,” Solid-StateCircuits, IEEE Journal of , vol.47, no.7, pp.1585,1593, July 2012

A True 1V 1µW Biomedical Front End with Reconﬁgurable ADC for Self powered Smarter IoT Healthcare Systems

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