Innovative Techniques for Testing and Diagnosing SoCs

We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

Innovative methods for Burn-In related Stress Metrics Computation

Burn-In equipment provide both external and internal stress to the device under test. External stress, such as thermal stress, is provided by a climatic chamber or by socket-level local temperature forcing tools, and aims at aging the circuit material, while internal stress, such as electrical stress, consists in driving the circuit nodes to produce a high internal activity. To support internal stress, Burn-In test equipment is usually characterized by large memory capabilities required to store precomputed patterns that are then sequenced to the circuit inputs. Because of the increasing complexity and density of the new generations of SoCs, evaluating the effectiveness of the patterns applied to a Device under Test (DUT) through a simulation phase requires long periods of time. Moreover, topology-related considerations are becoming more and more important in modern high-density designs, so a way to include this information into the evaluation has to be devised. In this paper we show a feasible solution to this problem: the idea is to load in the DUT a pattern not by shifting inside of it a bit at a time but loading the entire pattern at once inside of it; this kind of procedure allows for conservative stress measures, thus it fits for stress analysis purposes. Moreover, a method to take the topology of the DUT into account when calculating the activity metrics is proposed, so to obtain stress metrics which can better represent the activity a circuit is subject to. An automotive chip accounting for about 20 million of gates is considered as a case of study. Resorting to it we show both the feasibility and the effectiveness of the proposed methodology

Sizing and Energy Management of a Hybrid Locomotive Based on Flywheel and Accumulators

The French National Railways Company (SNCF) is interested in the design of a hybrid locomotive based on various storage devices (accumulator, flywheel, and ultracapacitor) and fed by a diesel generator. This paper particularly deals with the integration of a flywheel device as a storage element with a reduced-power diesel generator and accumulators on the hybrid locomotive. First, a power flow model of energy-storage elements (flywheel and accumulator) is developed to achieve the design of the whole traction system. Then, two energy-management strategies based on a frequency approach are proposed. The first strategy led us to a bad exploitation of the flywheel, whereas the second strategy provides an optimal sizing of the storage device. Finally, a comparative study of the proposed structure with a flywheel and the existing structure of the locomotive (diesel generator, accumulators, and ultracapacitors) is presented

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life

Self-lubricating coatings for high-temperature applications

Solid lubricants with maximum temperature capabilities of about 1100 C are known. Unfortunately, none of the solid lubricants with the highest temperature capabilities are effective below 400 C. However, research at NASA's Lewis Research Center shows that silver and stable fluorides such as calcium and barium fluorides act synergistically to provide lubrication from below room temperature to about 900 C. This paper describes plasma-sprayed composite coatings that contain these solid lubricants in combination with a metal-bonded chromium carbide. The lubricants control friction, and the carbide matrix provides wear resistance. Successful tests of these coatings as backup lubricants for compliant gas bearings in turbomachinery and as self-lubricating liners in a four-cylinder Stirling engine are discussed

Resistive Oxygen Gas Sensors for Harsh Environments

Resistive oxygen sensors are an inexpensive alternative to the classical potentiometric zirconia oxygen sensor, especially for use in harsh environments and at temperatures of several hundred °C or even higher. This device-oriented paper gives a historical overview on the development of these sensor materials. It focuses especially on approaches to obtain a temperature independent behavior. It is shown that although in the past 40 years there have always been several research groups working concurrently with resistive oxygen sensors, novel ideas continue to emerge today with respect to improvements of the sensor response time, the temperature dependence, the long-term stability or the manufacture of the devices themselves using novel techniques for the sensitive films. Materials that are the focus of this review are metal oxides; especially titania, titanates, and ceria-based formulations

Meta-heuristic algorithms in car engine design: a literature survey

Meta-heuristic algorithms are often inspired by natural phenomena, including the evolution of species in Darwinian natural selection theory, ant behaviors in biology, flock behaviors of some birds, and annealing in metallurgy. Due to their great potential in solving difficult optimization problems, meta-heuristic algorithms have found their way into automobile engine design. There are different optimization problems arising in different areas of car engine management including calibration, control system, fault diagnosis, and modeling. In this paper we review the state-of-the-art applications of different meta-heuristic algorithms in engine management systems. The review covers a wide range of research, including the application of meta-heuristic algorithms in engine calibration, optimizing engine control systems, engine fault diagnosis, and optimizing different parts of engines and modeling. The meta-heuristic algorithms reviewed in this paper include evolutionary algorithms, evolution strategy, evolutionary programming, genetic programming, differential evolution, estimation of distribution algorithm, ant colony optimization, particle swarm optimization, memetic algorithms, and artificial immune system

Composite Materials in Design Processes

The use of composite materials in the design process allows one to tailer a component’s mechanical properties, thus reducing its overall weight. On the one hand, the possible combinations of matrices, reinforcements, and technologies provides more options to the designer. On the other hand, it increases the fields that need to be investigated in order to obtain all the information requested for a safe design. This Applied Sciences Special Issue, “Composite Materials in Design Processes”, collects recent advances in the design methods for components made of composites and composite material properties at a laminate level or using a multi-scale approach