Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations

A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternat-ing U-shaped n/p– SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resis-tance. The folded U-shaped n/p– pillar uniformly distributes the electric field in the SJ drift region.The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of different carrier transport models are carried out with different doping profiles by calibrating the drift-diffusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and specific on-resistance (Ron,sp). The effect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the fixed ratio between the pillar width and the pillar height.It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-off ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V , thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device offers a specific on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the specific on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of offering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum specific on-resistance, and excellent FoM for sub - 100 V rating applications.Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Different scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping profile is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low specific on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V . Additionally, the scaled SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V , respectively.Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, specific on-resistance, and physical density for a higher integration in a CMOS architecture

Introducing the hybrid unipolar bipolar field effect transistor : the HUBFET

Modern commercial aircraft are becoming increasingly dependent on electrical power. More and more of the systems traditionally powered by hydraulics or pneumatics are being migrated to run on electricity. One consequence of the move towards electrical power is the increase in the storage capacity of the bat- teries used to supplement the power generation. The increase in battery size increases the maximum stress that a short circuit failure can put on the power distribution system. Although such failures are extremely rare, the fail safe switches in the distribution system must be capable of handling extremely high energy short circuits and turning off the power to protect the electrical systems from damage. Traditionally aircraft have used electromechanical relays in this role. However, they are large, heavy and slow to switch. As the potential power level is increased, the slow switching becomes more of a problem. The solution is a semiconductor switch. An IGBT can handle the high short circuit currents and switches fast enough to prevent short circuits damaging key systems. However, the inherent voltage drop in the forward current path significantly reduces its efficiency during nominal operation. A power MOSFET would be considerably more efficient than an IGBT during nominal operation. However, during high current surges, the ohmic behaviour of the switch leads to extremely high power loss and thermal failure. In this thesis a solution to this problem is presented. A new class of semiconductor device is proposed that has the highly efficient low current performance of the power MOSFET and the high current handling capability of the IGBT. The device has been named the Hybrid Unipolar Bipolar Field Effect Transistor or HUBFET. The HUBFET operates in unipolar mode, like a MOSFET, at low currents and in bipolar mode, like an IGBT, at high currents. The structure of the HUBFET is a merging of the MOSFET and IGBT. It is a vertical device with a traditional MOS gate structure, however the backside consists of alternating regions of both N-type and P-type doping. Through simulation the key on-state characteristics of the HUBFET have been shown. Fabricated test modules have been tested to validate the simulations and to show how the HUBFET can dynamically transistion from unipolar to bipolar mode during a short circuit event. Following the proof of concept the pattern of implants on the backside of the device that give the HUBFET its characteristic were investigated and potential improvements to the design were identified

Composite power semiconductor switches for high-power applications

It is predicted that 80 % of the world’s electricity will flow through power electronic based converters by 2030, with a growing demand for renewable technolo gies and the highest levels of efficiency at every stage from generation to load. At the heart of a power electronic converter is the power semiconductor switch which is responsible for controlling and modulating the flow of power from the input to the output. The requirements for these power semiconductor switches are vast, and include: having an extremely low level of conduction and switching losses; being a low source of electromagnetic noise, and not being susceptible to external Electromagnetic Interference (EMI); and having a good level of ruggedness and reliability. These high-performance switches must also be economically viable and not have an unnecessarily large manufacturing related carbon footprint. This thesis investigates the switching performance of the two main semiconductor switches used in high-power applications — the well-established Silicon (Si)-Insulated-Gate Bipolar Transistor (IGBT) and the state-of-the-art Wide-Bandgap (WBG) Silicon-Carbide (SiC)-Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET). The SiC-MOSFET is ostensibly a better device than the Si-IGBT due to the lower level of losses, however the cost of the device is far greater and there are characteristics which can be troublesome, such as the high levels of oscillatory behaviour at the switching edges which can cause serious Electromagnetic Compatibility (EMC) issues. The operating mechanism of these devices, the materials which are used to make them, and their auxiliary components are critically analysed and discussed. This includes a head-to-head comparison of the two high-capacity devices in terms of their losses and switching characteristics. The design of a high-power Double-Pulse Test Rig (DPTR) and the associated high-bandwidth measurement platform is presented. This test rig is then extensively used throughout this thesis to experimentally characterise the switching performance of the aforementioned high-capacity power semiconductor devices. A hybrid switch concept — termed “The Diverter” — is investigated, with the motivation of achieving improved switching performance without the high-cost of a full SiC solution. This comprises a fully rated Si-IGBT as the main conduction device and a part-rated SiC-MOSFET which is used at the turn-off. The coordinated switching scheme for the Si/SiC-Diverter is experimentally examined to determine the required timings which yield the lowest turn-off loss and the lowest level of oscillatory behaviour and other EMI precursors. The thermal stress imposed on the part-rated SiC-MOSFET is considered in a junction temperature simulation and determined to be negligible. This concept is then analysed in a grid-tied converter simulation and compared to a fully rated SiC-MOSFET and Si-IGBT. A conduction assistance operating mode, which solely uses the part-rated SiC-MOSFET when within its rating, is also investigated. Results show that the Diverter achieves a significantly lower level of losses compared to a Si-IGBT and only marginally higher than a full SiC solution. This is achieved at a much lower cost than a full SiC solution and may also provide a better method of achieving high-current SiC switche

Development of a fault tolerant MOS field effect power semiconductor switching transistor

This work describes the development of a semiconductor switch to replace an electromechanical contactor as used within the electrical power distribution system of the More Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The MEA is safety critical and therefore requires highest reliability components and systems, but subsequent to a short circuit load fault the electro-mechanical contactor switch often welds shut. This risk is increased when using high discharge energy lithium ion dc batteries. Predominately the semiconductor switch controls inductive loads and is required to safely turn off current of up to 10 times the nominal level during sporadic load fault events. The switch requires the lowest static loss (lowest on state resistance), but also the lowest dynamic loss (losses due to the switching event). Presently, unipolar devices provide the lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which is sized to suit the fault current, but at relatively high cost in terms of silicon area. The resultant area is typically achieved by several die connected in parallel, unfortunately, such a solution suffers from current share imbalance and the potential of cascade die failure. The use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid which proves challenging if the load current is to be shared appropriately during fault switching in order to prevent failure. Some form of single MOS (Metal Oxide Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore required to ensure highest reliability through a non latching design which offers lowest losses under all conditions and achieves an even temperature distribution. In this work the novel concept of the integrated hybrid device has been investigated at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises a novel merged Schottky p-type injector to provide self biased entry into a reduced static loss bipolar state in the event of high fault current. The device achieves a specific on state resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon limit line and requires half the area of a traditional unipolar MOSFET to conduct fault current. During comparative standard unclamped inductive switching trials, the hybrid device provides a self clamping action which enables increased inductive energy switching (higher inductance and/or higher load current), relative to that achieved by either the MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically >10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device is latch up free across the operational temperature range of T=233 K to 400 K. A viable charge balanced structure to increase the BV rating to approximately 600 V is also proposed. The resulting performance of the single gated, self biased, hybrid, utilising a novel merged Schottky/P type injector, could lead to a new class of rugged MOS gated power switching devices in silicon and potentially silicon carbide

High power wide bandgap cascode switching circuits

Emerging wide bandgap (WBG) power transistors are capable of improving the efficiency of mains voltage power electronic circuits. Several commercial WBG transistors are now available, but all exhibit undesirable gate drive characteristics. The cascode circuit has been suggested as a solution to this problem: WBG cascodes improve the switching speed, gate characteristics and noise immunity of devices, at the expense of greater on-state resistance. WBG cascodes have not, however, been widely accepted in commercial applications. Previous research has typically been too application-specific, with little practical information available for design engineers wishing to use them. This thesis addresses these shortcomings through a comprehensive investigation of practical design considerations for switch-mode cascode circuits. A SPICE simulation and simplified mathematical model are developed as design tools to give a detailed insight into cascode hard-switching behaviour and to aid cascode optimisation and device selection. The effects of the cascode configuration on static (DC) device performance are quantified for a silicon super-junction (SJ) metal-oxide-semiconductor field-effect transistor (MOSFET), silicon carbide (SiC) junction field-effect transistor JFET and SiC MOSFET. The on-state resistance penalty of the cascode configuration is shown to be modest and potentially mitigated by careful selection of HV transistor gate bias. There are few advantages to using silicon SJ MOSFETs in a cascode configuration, but both SiC MOSFET and JFET cascodes benefit from improved gate drive, reverse conduction and switching characteristics. SiC MOSFETs are shown to be better suited to efficient high temperature operation, while SiC JFETs are more appropriate for high current applications. Cascode switching losses are shown to be reduced compared to standalone devices, although reverse recovery losses can counteract this. Methods of controlling switching transients using gate resistors or feedback capacitors are investigated and shown to be effective. The effects of stray inductance on cascode switching are quantified experimentally for the first time. This corroborates other work and informs the layout of cascode circuits. The resilience of cascodes to severe $\frac{dV}{dt}$ is also demonstrated. The findings of this thesis are summarised in a practical design guide aimed at design engineers who wish to use this useful circuit

Analysis of dynamic performance and robustness of silicon and SiC power electronics devices

The emergence of SiC power devices requires evaluation of benefits and issues of the technology in applications. This is important since SiC power devices are still not as mature as their silicon counterparts. This research, in its own capacity, highlights some of the major challenges and analyzes them through extensive experimental measurements which are performed in many different conditions seeking to emulate various applications scenarios. It is shown that fast SiC unipolar devices, inherently reduce the switching losses while maintain low conduction losses comparable with contemporary bipolar technologies. This translates into lower temperature excursions and an enhanced conversion efficiency. However, such high switching rates may trigger problems in the device utilizations. The switching rates influenced by the device input capacitance can cause significant ringing in the output, especially in SiC SBDs. Measurements show that switching rate of MOSFETs increases with increasing temperature in turn on and reduces in turn off. Hence, the peak voltage overshoot and oscillation severity of the SiC SBD increases with temperature during diode turn off. This temperature dependence reduces at the higher switching rates. So accurate analytical models are developed for predicting the switching energy in unipolar SiC SBDs and MOSFET pairs and bipolar silicon PiN and IGBT pairs. A key parameter for power devices is electrothermal robustness. SiC MOSFETs have already demonstrated such merits compared to silicon IGBTs, however not for MOSFET body diodes. This research has quantified this in comparison with the similarly rated contemporary device technologies like CoolMOS. In a power MOSFET, high switching rates coupled with the capacitance of drain and body causes a displacement current in the resistive path of P body, inducing a voltage on base of the parasitic NPN BJT which might forward bias it. This may lead to latch up and destruction if the thermal limits are surpassed. Hence, trade offs between switching energy and electrothermal robustness are explored for the silicon, SiC and superjunction power MOSFETs. Measurements show that performance of body diodes of SiC MOSFETs is the most efficient due to least reverse recovery. The minimum forward current for inducing dynamic latch up decreases with increasing voltage, switching rate and temperature for all technologies. The CoolMOS exhibited the largest latch up current followed by the SiC and silicon power MOSFETs. Another problem induced by high switching rates is the electrical coupling between complementing devices in the same phase leg which manifests as short circuits across the DC link voltage. This has been understood for silicon IGBTs with known corrective techniques, however it is seen that due to smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot through currents in spite of higher switching rates and a lower threshold voltage. Measurements show that the shoot through current exhibits a positive temperature coefficient for both technologies the magnitude of which is higher for the silicon IGBT. The effectiveness of common techniques of mitigating shoot through is also evaluated, showing that solutions are less effective for SiC MOSFET because of the lower threshold voltages and smaller margins for a negative gate bias

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Contributions to the design of power modules for electric and hybrid vehicles: trends, design aspects and simulation techniques

314 p.En la última década, la protección del medio ambiente y el uso alternativo de energías renovables están tomando mayor relevancia tanto en el ámbito social y político, como científico. El sector del transporte es uno de los principales causantes de los gases de efecto invernadero y la polución existente, contribuyendo con hasta el 27 % de las emisiones a nivel global. En este contexto desfavorable, la electrificación de los vehículos de carretera se convierte en un factor crucial. Para ello, la transición de la actual flota de vehículos de carretera debe ser progresiva forzando la investigación y desarrollo de nuevos conceptos a la hora de producir vehículos eléctricos (EV) y vehículos eléctricos híbridos (HEV) más eficientes, fiables, seguros y de menor coste. En consecuencia, para el desarrollo y mejora de los convertidores de potencia de los HEV/EV, este trabajo abarca los siguientes aspectos tecnológicos: - Arquitecturas de la etapa de conversión de potencia. Las principales topologías que pueden ser implementadas en el tren de potencia para HEV/EV son descritas y analizadas, teniendo en cuenta las alternativas que mejor se adaptan a los requisitos técnicos que demandan este tipo de aplicaciones. De dicha exposición se identifican los elementos constituyentes fundamentales de los convertidores de potencia que forman parte del tren de tracción para automoción.- Nuevos dispositivos semiconductores de potencia. Los nuevos objetivos y retos tecnológicos solo pueden lograrse mediante el uso de nuevos materiales. Los semiconductores Wide bandgap (WBG), especialmente los dispositivos electrónicos de potencia basados en nitruro de galio (GaN) y carburo de silicio (SiC), son las alternativas más prometedoras al silicio (Si) debido a las mejores prestaciones que poseen dichos materiales, lo que permite mejorar la conductividad térmica, aumentar las frecuencias de conmutación y reducir las pérdidas.- Análisis de técnicas de rutado, conexionado y ensamblado de módulos de potencia. Los módulos de potencia fabricados con dies en lugar de dispositivos discretos son la opción preferida por los fabricantes para lograr las especificaciones indicadas por la industria de la automoción. Teniendo en cuenta los estrictos requisitos de eficiencia, fiabilidad y coste es necesario revisar y plantear nuevos layouts de las etapas de conversión de potencia, así como esquemas y técnicas de paralelización de los circuitos, centrándose en las tecnologías disponibles.Teniendo en cuenta dichos aspectos, la presente investigación evalúa las alternativas de semiconductores de potencia que pueden ser implementadas en aplicaciones HEV/EV, así como su conexionado para la obtención de las densidades de potencia requeridas, centrándose en la técnica de paralelización de semiconductores. Debido a la falta de información tanto científica como comercial e industrial sobre dicha técnica, una de las principales contribuciones del presente trabajo ha sido la propuesta y verificación de una serie de criterios de diseño para el diseño de módulos de potencia. Finalmente, los resultados que se han extraído de los circuitos de potencia propuestos demuestran la utilidad de dichos criterios de diseño, obteniendo circuitos con bajas impedancias parásitas y equilibrados eléctrica y térmicamente. A nivel industrial, el conocimiento expuesto en la presente tesis permite reducir los tiempos de diseño a la hora de obtener prototipos de ciertas garantías, permitiendo comenzar la fase de prototipado habiéndose realizado comprobaciones eléctricas y térmicas