An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

Design of a Comparator and an Amplifier in CMOS using standard logic gates

Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe- sizability, as well as the voltage scalability between technologies. In this work a general pur- pose standard-cell-based voltage comparator and amplifier are presented. The objective is to design a general purpose standard-cell-based comparator and ampli- fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving some of the specifications of the studied topologies. Various simulation testbenches were made to test the studied topologies of comparators and amplifiers, in which the results were compared. The top performing standard-cell com- parator and amplifier were then modified. After successfully designing the comparator, it was used in the design of an opamp-less Sigma-Delta modulator (ΣΔM). The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of 10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz. The proposed amplifier is a single-path three-stage inverter-based operational transcon- ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of 63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW, considering a load of 1 pF. The proposed comparator was employed in the ΣΔM with a standard-cell based edge- triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of 2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple- tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são apresentados um comparador de tensão e um amplificador utilizando portas lógicas. O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por- tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me- lhoramento de algumas das especificações das mesmas. Foram realizados vários bancos de teste para testar as topologias estudadas de compa- radores e amplificadores, em que os resultados foram comparados. As topologias de compa- radores e amplificadores de portas lógicas com melhor performance foram então modificadas. Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula- dor Sigma-Delta (ΣΔM) opamp-less. O comparador proposto é um OR-AND-Inversor com duas entradas e saídas, que apre- senta um atraso de 109 ps, offset estático na entrada de 591 μV, offset aleatório de 10.42 μV, enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz O amplificador proposto é um amplificador operacional de transcondutância single- path three-stage inverter-based com um loop ativo de realimentação do modo-comum, que apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF. O comparador proposto foi aplicado no ΣΔM com um flip-flop edge-triggered baseado em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7 μW

Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

SMART-E-PTDC/CTM-PAM/04012/2022, IDS-PAPER-PTDC/CTM-PAM/4241/2020 and PEST (CTS/UNINOVA)-UIDB/00066/2020. This work also received funding from the European Community’s H2020 program [Grant Agreement No. 716510 (ERC-2016-StG TREND) and 952169 (SYNERGY, H2020-WIDESPREAD-2020-5, CSA)]. Publisher Copyright: © 2022 by the authors.In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.publishersversionpublishe

A Low-Power Capacitive Transimpedance D/A Converter

This thesis proposes a new low-power and low-area DAC for single-slope ADCs used in CMOS image sensors. With increase in resolution requirements for ADCs, conventional DAC architectures suffered the limitation of either large area or high power consumption with higher resolution scaling. Thus, the proposed capacitive transimpedance amplifier DAC (CTIA DAC) could solve this by offering the resolution requirement required without taking a hit on the area or power budget. The thesis has been structured in the following manner: The first chapter introduces image sensors in general and talks about progression through different image sensors and pixel architectures that have been used through the years. It also explains the operation of a CMOS image sensor from a paper published from Sony on high-speed image sensors. The second chapter presents the importance and role of DACs in CMOS image sensors and briefly explains a few commonly used DAC architectures in image sensors. It explains the advantages and disadvantages of present architectures and leads the discussion towards the development of the proposed DAC. The third chapter gives an overview of the CTIA DAC and explains the working of the different circuit blocks that are used to implement the proposed DAC. Chapter Four explains the design approach for the blocks explained in Chapter Three. It presents the critical design choices that were made for overall performance of the DAC. Results of individual blocks and the DAC as a whole are presented and compared against other recently published DAC papers. The final chapter summarizes some key results of the design and talks about the scope for future work and improvement

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

Analogue hardware based algorithm for low-power and low-voltage position measurement systems with enhanced resolution

Position measurement systems are used in a wide variety of applications based on different sensing principles. Whatever the application or sensing method, they all share common issues of accuracy, robustness and power consumption. This thesis concentrates on two aspects of sensor interface design in order to achieve a very low power consumption for position measurement systems, in order to optimise their use for battery applications. A new architecture and optimized components have been investigated with regard to low power and low voltage operation. The architecture establishes typical properties of position measurement systems such as linearization and resolution enhancement. A new method for resolution enhancement in respect of low power and low voltage system requirements is proposed within this work. The same major requirements are also fulfilled on a component level. On an architectural level, the method utilizes signal symmetry provided by the sensor signal. A very common output signal of position measurement sensor elements establishes a sine and a cosine waveform. With folding and signal transformation techniques these signals are coarse converted and pre- processed before A/D conversion. As a result, the number of components is reduced and a significant amount of power is saved. Many position measurement systems linearize the sensor element signals by digital computation. This work proposes a method of linearization within the A/D converter. The advantage is that no extra power consumption is involved because no additional elements are inserted into the A/D converter. By using a non-linear resistor network that composes the sine and cosine sensor signal, a linearized output is obtained. As a result the linearization algorithm is realised by an analogue hardware circuit. This has the added benefit of reducing the circuit noise, a common problem with digital circuits. In addition to the architectural level design, new components realized as integrated circuit cells, contribute to a reduction of the overall power consumption. Both, the power supply voltage and the power supply current are significantly reduced. A trade-off between performance and reduction of power consumption has been the basis of the circuit design. Circuit components that determine the minimum power supply voltage have been the subject of a thorough investigation in respect of sub-threshold or moderate inversion operation. As a result, a power supply voltage range smaller than given by the fundamental limits for strong inversion operation can be chosen. These components were realized as a physical cell design and implemented in the form of a test chip. Test results are reported that demonstrate the practical performance of the overall architecture and individual components. A new error model has been developed for the overall sensor system in order to investigate the influence of parameter deviation and inherent errors. The model has been used in simulation studies that demonstrate the overall accuracy and robustness of the design. The thesis concludes with a summary of the major achievements and an evaluation, in the form of a comparison with existing systems