Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications

Ny forskning innenfor feltet trådløse sensornettverk åpner for nye og innovative produkter og løsninger. Biomedisinske anvendelser er blant områdene med størst potensial og det investeres i dag betydelige beløp for å bruke denne teknologien for å gjøre medisinsk diagnostikk mer effektiv samtidig som man åpner for fjerndiagnostikk basert på trådløse sensornoder integrert i et ”helsenett”. Målet er å forbedre tjenestekvalitet og redusere kostnader samtidig som brukerne skal oppleve forbedret livskvalitet som følge av økt trygghet og mulighet for å tilbringe mest mulig tid i eget hjem og unngå unødvendige sykehusbesøk og innleggelser. For å gjøre dette til en realitet er man avhengige av sensorelektronikk som bruker minst mulig energi slik at man oppnår tilstrekkelig batterilevetid selv med veldig små batterier. I sin avhandling ” Ultra Low power Digital Circuit Design for Wireless Sensor Network Applications” har PhD-kandidat Farshad Moradi fokusert på nye løsninger innenfor konstruksjon av energigjerrig digital kretselektronikk. Avhandlingen presenterer nye løsninger både innenfor aritmetiske og kombinatoriske kretser, samtidig som den studerer nye statiske minneelementer (SRAM) og alternative minnearkitekturer. Den ser også på utfordringene som oppstår når silisiumteknologien nedskaleres i takt med mikroprosessorutviklingen og foreslår løsninger som bidrar til å gjøre kretsløsninger mer robuste og skalerbare i forhold til denne utviklingen. De viktigste konklusjonene av arbeidet er at man ved å introdusere nye konstruksjonsteknikker både er i stand til å redusere energiforbruket samtidig som robusthet og teknologiskalerbarhet øker. Forskningen har vært utført i samarbeid med Purdue University og vært finansiert av Norges Forskningsråd gjennom FRINATprosjektet ”Micropower Sensor Interface in Nanometer CMOS Technology”

Novel IC designs with 32 nm Independent-Gate FinFET

Electrical EngineeringThe semiconductor industry is confronted with serious challenges as the push continues toward scaling transistors into the 22-nm technology node and beyond. The most important among these challenges is the diminishing gate control over the channel, which manifests itself in the form of the increased short-channel effects (SCE) and leakage currents. One approach to countering these effects is introducing new materials for improved performance, either into the gate stack, the channel, or the source/drain extension regions. However, even with the introduction of these new materials, leakage will continue to be a serious problem. Hence, alter device architecture are being explored which processes inherently better robustness to SCE. Among this alternatives, multiple-gate FETs, also known as FinFET or gate wrap-around FETs, are emerging as promising candidates. In a FinFET, the gate wraps around a thin slice of silicon, also known as a ???fin???, and current flows along the top and side surface of the fin. This wrap-around nature of the gate enhances the gate control over the channel, thus reducing the SCE and leakage currents. Furthermore, fabrication of FinFET is compatible with that of conventional CMOS, thus making possible very rapid deployment to manufacturing. From a circuit-design perspective, FinFET provides IC designer with more options to innovate. For instance, FinFET device can directly substitute the CMOS in the existing applications by using the shorted-gate FinFET in which two FinFET gates are tied together. Additionally, the low-power mode of FinFET device in which the back-gate bias is tied to a reverse-bias voltage is often employed in the low-power design in that it can reduce subthreshold leakage. Last but not least, the independent-gate FinFET emerges as an interesting device so that IC designers have a variety of choices to flexibly use the two gates of FinFET for difference tasks. In this thesis, independent-gate FinFET are our concern with two designs being included. The first work presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, a boosting structures is developed to improve the signal propagation on interconnect significantly. In the second work, a digital voltage sensor design is illustrated. Based on the operation of a p-type FinFET in low-power mode and independent-gate mode, a new technique for designing a controllable delay element (CDE) with high linearity is presented. Then, we develop a 9-bit digital voltage sensor with a voltage range of 0.7 ??? 1.1 V and 50 mV resolution. The proposed voltage sensor can operate with ultra-low power, a wide voltage range, and fairly high frequency.ope

INTEGRATED CIRCUITS FOR HIGH ENERGY PHYSICS EXPERIMETNS

Integrated Circuits are used in most people\u2019s lives in the modern societies. An important branch of research and technology is focused on Integrated Circuit (IC) design, fabrication, and their efficient applications; moreover most of these activities are about commercial productions with applications in ambient environment. However the ICs play very important role in very advance research fields, as Astronomy or High Energy Physics experiments, with absolutely extreme environments which require very interdisciplinary research orientations and innovative solutions. For example, the Fast TracKer (FTK) electronic system, which is an important part of triggering system in ATLAS experiment at European Organization for Nuclear Research (CERN), in every second of experiment selects 200 interesting events among 40 millions of total events due to collision of accelerated protons. The FTK function is based on ICs which work as Content Addressable Memory (CAM). A CAM compares the income data with stored data and gives the addresses of matching data as an output. The amount of calculation in FTK system is out of capacity of commercial ICs even in very advanced technologies, therefore the development of innovative ICs is required. The high power consumption due to huge amount of calculation was an important limitation which is overcome by an innovative architecture of CAM in this dissertation. The environment of ICs application in astrophysics and High Energy Physics experiments is different from commercial ICs environment because of high amount of radiation. This fact started to get seriously attention after the first \u201cTelstar I\u201d satellite failure because of electronic damages due to radiation effects in space, and opened a new field of research mostly about radiation hard electronics. The multidisciplinary research in radiation hard electronic field is about radiation effects on semiconductors and ICs, deep understanding about the radiation in the extreme environments, finding alternative solutions to increase the radiation tolerance of electronic components, and development of new simulation method and test techniques. Chapter 2 of this dissertation is about the radiation effects on Silicon and ICs. Moreover, In this chapter, the terminologies of radiation effects on ICs are explained. In chapter 3, the space and high energy physics experiments environments, which are two main branches of radiation hard electronics research, are studied. The radiation tolerance in on-chip circuits is achieving by two kinds of methodology: Radiation Hardening By Process (RHBP) and Radiation Hardening By Design (RHBD). RHBP is achieved by changing the conventional fabrication process of commercial ICs. RHBP is very expensive so it is out of budget for academic research, and in most cases it is exclusive for military application, with very restricted rules which make the access of non-military organizations impossible. RHBD with conventional process is the approach of radiation hard IC design in this dissertation. RHBD at hardware level can be achieved in different ways: \u2022 System level RHBD: radiation hardening at system level is achieved by algorithms which are able to extract correct data using redundant information. \u2022Architecture level RHBD: some hardware architectures are able to prevent of lost data or mitigate the radiation effects on stored data without interfacing of software. Error Correction Code (ECC) circuits and Dual Interlocked storage CEll (DICE) architecture are two examples of RHBD at architecture level. \u2022 Circuit level RHBD: at circuit level, some structures are avoided or significantly reduced. For example, feedback loops with high gain are very sensitive to radiation effects. \u2022 Layout level RHBD: there are also different solutions in layout design level to increase the radiation tolerance of circuits. Specific shapes of transistor design, optimization of the physical distance between redundant data and efficient polarization of substrate are some techniques commonly used to increase significantly the radiation tolerance of ICs. An innovative radiation hard Static Random Access Memory (SRAM), designed in three versions, is presented in chapter 4. The radiation hardening is achieved by RHBD approach simultaneously at architecture, circuit and layout levels. Complementary Metal-Oxide-Semiconductor (CMOS) 65 nm is the technology of design and the prototype chip is fabricated at Taiwan Semiconductor Manufacturing Company (TSMC). Chapter 5 is about the development of simulation models that can help to predict the radiation effect in the behavior of SRAM block. The setup system developed to characterize the radiation hard SRAM prototype chip is presented in Chapter 5. The setup system gives the possibility of testing the prototype exposed under radiation in a vacuum chamberand regular laboratory environment. Chapter 6 is about the contribution of this dissertation on FTK project and the conclusion of all research activities is shown in the final part of this dissertation. The research activities of this dissertation in supported by Italian National Institute for Nuclear Physics (INFN) as part of CHIPIX65 project and RD53 collaboration at CERN

Improving the Reliability of Microprocessors under BTI and TDDB Degradations

Reliability is a fundamental challenge for current and future microprocessors with advanced nanoscale technologies. With smaller gates, thinner dielectric and higher temperature microprocessors are vulnerable under aging mechanisms such as Bias Temperature Instability (BTI) and Temperature Dependent Dielectric Breakdown (TDDB). Under continuous stress both parametric and functional errors occur, resulting compromised microprocessor lifetime. In this thesis, based on the thorough study on BTI and TDDB mechanisms, solutions are proposed to mitigating the aging processes on memory based and random logic structures in modern out-of-order microprocessors. A large area of processor core is occupied by memory based structure that is vulnerable to BTI induced errors. The problem is exacerbated when PBTI degradation in NMOS is as severe as NBTI in PMOS in high-k metal gate technology. Hence a novel design is proposed to recover 4 internal gates within a SRAM cell simultaneously to mitigate both NBTI and PBTI effects. This technique is applied to both the L2 cache banks and the busy function units with storage cells in out-of-order pipeline in two different ways. For the L2 cache banks, redundant cache bank is added exclusively for proactive recovery rotation. For the critical and busy function units in out-of-order pipelines, idle cycles are exploited at per-buffer-entry level. Different from memory based structures, combinational logic structures such as function units in execution stage can not use low overhead redundancy to tolerate errors due to their irregular structure. A design framework that aims to improve the reliability of the vulnerable functional units of a processor core is designed and implemented. The approach is designing a generic function unit (GFU) that can be reconfigured to replace a particular functional unit (FU) while it is being recovered for improved lifetime. Although flexible, the GFU is slower than the original target FUs. So GFU is carefully designed so as to minimize the performance loss when it is in-use. More schemes are also designed to avoid using the GFU on performance critical paths of a program execution

Filière technologique hybride InGaAs/SiGe pour applications CMOS

High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe

Double-gate single electron transistor : modeling, design & evaluation of logic architectures

Dans les années à venir, l'industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine « Beyond CMOS », ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. En effet, l'émergence du caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d'envisager la réalisation de remplaçants potentiels des transistors ou de cellules mémoire à haute densité d'intégration, basse consommation. L'objectif principal de ce travail de thèse est d'explorer et d'évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DG-SETs dans une approche « cellules standards » ; et iii) l'exploration d'architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l'aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en termes de consommation d'énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques

A design concept for radiation hardened RADFET readout system for space applications

Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions