A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

Low-Voltage, Low-Area, nW-Power CMOS Digital-Based Biosignal Amplifier

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 μVRMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR

Low-voltage, low-area, nW-power CMOS digital-based biosignal amplifier

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22× times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 μVRMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR

Noise Efficient Integrated Amplifier Designs for Biomedical Applications

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2

A low noise amplifier suitable for biomedical recording analog front-end in 65nm CMOS technology

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd

심전도 감시 분야를 위한 저전력 신호 특화된 축차 비교형 아날로그-디지털 변환기의 설계

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 김수환.Electrocardiography is an indispensable tool employed for diagnosis of cardiovascular diseases. When electrocardiograms (ECGs) need to be monitored for a long time, e.g. to diagnose arrhythmia, a device has to be worn or implanted under the skin, which requires low energy consumption. Successive approximation register analog-to-digital converters (SAR ADCs) have been especially preferred in low power applications, while the recent trend of ADC designs shows that the SAR ADCs find a much wide range of applications, and are the most versatile ADC architecture. The subject of the dissertation is the design of a signal-specific SAR ADC scheme that reduces the power consumption by exploiting the characteristics of the input signal of a particular type whose signal activity is low on average and dichotomous, as best exemplified by ECGs. This dissertation presents a 1.8-V 10-bit 1-kS/s low-power SAR ADC with the proposed signal-specific switching algorithm. The proposed adaptive switching algorithm has two operation modes suitable for the dichotomous activity of the ECG: full switching mode that resolves the full range of the input as an ordinary SAR ADC, and reduced switching mode that assumes 5 MSBs will not change and samples just the rest LSB portion and resolves it in 5 bitcycles. The reduced number of bitcycles yields saving in switching power consumption. For smooth mode change adaptive to the input signal activity, an additional function in each mode, viz., MSBs tracking in full switching mode and LSBs extrapolation in reduced switching mode, runs concurrently with the respective main operation. A behavioral model of the proposed SAR ADC with the segmented capacitor digital-to-analog converter (CDAC) topology was created in MATLAB and was used in the tests, which verified the function and effectiveness of the adaptive switching algorithm. The model describes the evolution of all internal node voltages in the CDAC by each switching action, from which the charge variation in each capacitor and the switching energy consumption can be computed. The model was extensively used for the development and analysis of the idea. The 5-bit size of the MSB section was determined from the simulation results with the behavioral model. A prototype chip was fabricated in 0.18-μm CMOS technology. Measurements with an ECG type input proved the suitability of the adaptive switching for ECG monitoring. The power reduction by the adaptive switching in each of comparator, logic, and DAC power domains was calculated from the measurements of both cases of the adaptive-switching and fixed-full-switching operations, the latter of which is equivalent to the conventional SAR ADC operation. It achieved a reduction in comparator power consumption by 39%. The DAC power, i.e. the switching power consumed in the CDAC, achieved a reduction by 1.28 nW, which is close to the result of the behavioral model simulation. The reduction in the logic power domain was 12%. In terms of total power consumption, the adaptive switching consumed 91.02 nW while the fixed full switching consumed 107.51 nW. The reduction corresponds to 15.3% in proportion. In addition, the intrinsic performance of the ADC was measured using a sinusoidal input. It achieved a signal-to-noise-and-distortion ratio of 56.24 dB and a spurious-free dynamic range of 62.00 dB. The maximum differential nonlinearity of +0.39/−1 LSBs and maximum integral nonlinearity of +0.86/−1.5 LSBs were measured. The main source of the nonlinearity is the capacitor mismatch in the CDAC.심전도는 심혈관계 질환의 진단을 위한 중요한 자료로서 감시 및 기록된다. 때로 부정맥 진단 등을 위하여 심전도를 오랜 시간 관찰해야 할 경우, 착용 가능한(웨어러블) 장비나 체내에 이식할 수 있는 장비를 사용해야 하는데, 이들은 전력 소비가 적어야 한다. 축차 비교형 아날로그-디지털 변환기(SAR ADC)는 저전력 응용 분야에서 주로 선호한 구조였으나 최근 아날로그-디지털 변환기 설계의 추세는 SAR ADC가 훨씬 넓은 응용 분야에 적용 가능하며 가장 넓은 범용성을 가진 구조임을 보여준다. 본 논문의 주제는 심전도 신호처럼 양분된 신호 활성도를 가지면서 평균 신호 활성도는 낮은 유형의 신호를 대상으로, 이 특성을 이용하여 전력의 소비를 낮추는 신호 특화된 스위칭 기법을 적용한 SAR ADC 설계이다. 본 논문에서는 신호 특화된 기법을 적용한 1.8V, 10 bit, 1kS/s의 저전력 SAR ADC 설계를 제시한다. 제안하는 적응형 스위칭 기법은 ECG의 양분된 신호 활성도 특성에 맞추어, 일반적인 SAR ADC처럼 입력의 전체 범위를 처리하는 full switching mode와, 5-bit MSB code가 변하지 않을 것이라는 가정하에 나머지 LSB 부분만 샘플링하고 처리하는 reduced switching mode의 두 가지 동작 모드를 가진다. 입력 신호 활성도에 따라 유연하게 동작 모드를 전환하기 위하여, full switching mode는 MSBs tracking, reduced switching mode는 LSBs extrapolation라는 부가 기능이 각 모드의 주 기능과 함께 동작한다. 제안한 SAR ADC의 behavioral model을 MATLAB에서 만들었고, 이를 이용한 여러 테스트에서 적응형 스위칭 기법의 기능과 효과를 검증하였다. 이 behavioral model은 SAR ADC 내에 있는 segmented CDAC의 모든 내부 node 전압의 변화를 개별 스위칭 동작에 대해 기술하므로, 이를 이용하여 각 캐패시터에 저장된 전하의 변화량이나 스위칭 에너지 소비량을 계산할 수 있다. 이 model을 idea 개발 및 분석에 광범위하게 이용하였다. 0.18μm CMOS 공정에서 시제품 칩을 제작하였다. 심전도 유형의 입력 신호를 이용한 측정을 통해 제안한 적응형 스위칭 기법이 심전도 감시 분야에 적합함을 증명하였다. 제안한 기법으로 얻어지는 ADC의 전력 감소는 제안한 적응형 스위칭으로 동작한 경우와 full switching mode로 고정된 경우(기존의 SAR ADC 동작에 해당)에서 비교기, 논리 회로, DAC 3개 영역의 전력 측정값에서 계산하였다. 비교기 회로의 전력 소비는 39% 줄었다. DAC에서 소비된 전력, 즉 CDAC의 switching 전력 소비량은 1.28 nW가 감소했는데, behavioral model의 simulation 결과와 비슷한 값이다. 논리 회로 영역에서는 12%가 줄었다. 전체 전력 소비는 적응형 스위칭 기법을 적용했을 때 91.02 nW, full switching mode로 고정했을 때 107.51 nW으로 15.3% 감소하였다. 또, sine 입력을 이용하여 설계한 ADC의 기본 성능을 측정하였다. 그 결과 56.24dB의 SNDR과 62.00 dB의 SFDR을 얻었고, 비선형성 지표인 최대 DNL과 INL은 각각 +0.39/−1 LSBs와 +0.86/−1.5 LSBs 을 얻었다. 이 비선형성 특성은 주로 CDAC 내의 캐패시터 미스매치에 기인한 것이다.Chapter 1 Introduction 1 1.1 Electrocardiography 1 1.2 Recent Trends in SAR ADC Designs 4 1.3 Dissertation Contributions and Organization 7 Chapter 2 SAR ADC Operation and Design Issues 9 2.1 Operation Principle 9 2.2 Switching Algorithms for Power Reduction 12 2.2.1 Computation of Switching Energy Consumption 12 2.2.2 Conventional Charge-Redistribution Switching 15 2.2.3 Split-Capacitor Switching 16 2.2.4 Energy-Saving Switching 18 2.2.5 Set-and-Down Switching 21 2.2.6 Merged-Capacitor Switching 22 2.3 Offset and Noise 25 2.4 Linearity 29 2.5 Area 32 Chapter 3 Adaptive Switching SAR ADC for ECG Monitoring Applications 34 3.1 ECG Characteristics and Readout Circuit 34 3.1.1 ECG Signals and Characteristics 34 3.1.2 ECG Readout Circuit 35 3.2 Related Signal-Specific Works 37 3.2.1 SAR ADC with a Bypass Window for Neural Signals 37 3.2.2 LSB-First Successive Approximation 39 3.3 Adaptive Switching 41 3.3.1 Motivation 41 3.3.2 Preliminary Test 42 3.3.3 Algorithm 46 3.3.4 Energy Consumption of SAR ADC with Segmented CDAC 54 3.3.5 Behavioral Model Simulations 59 3.3.6 Consideration on Other Applications 75 3.4 Circuit Implementation 76 3.4.1 Overview 76 3.4.2 Comparator and CDAC 78 3.4.3 Adaptive Switching Logic 81 Chapter 4 Prototype Measurements 86 4.1 Fabrication and Experiment Setup 86 4.2 Measurements 88 4.2.1 Power Reduction Measurement with ECG-Type Input 88 4.2.2 Intrinsic Performance Measurement with Sinusoidal Input 93 4.2.3 Summary of the Measurements and Specifications 96 Chapter 5 Conclusion 98 Bibliography 101 Abstract in Korean 107Docto

PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND

The primary objective of this research work is the development of a low power single-lead ECG analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient gain and frequency control mechanism and a low complexity classifier for the detecting asystole, extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the design of a compact single-lead wearable/portable devices with ultra-low-power consumption and in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an efficient automatic gain control mechanism with minimal area overhead and consuming power in the order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR), hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter design, the low pass cut-off frequency is prone to deviate from its nominal value across process and temperature variations. Therefore, post-fabrication calibration is essential, before the signal is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher frequencies into the bandwidth for classification of ECG signals, to switch to low resolution processing, hence saving power and enhances battery lifetime. Another short-coming noticed in the literature published so far is that the classification algorithm is implemented in digital domain, which turns out to be a power hungry approach. Moreover, Although analog domain implementations of QRS complexes detection schemes have been reported, they employ an external micro-controller to determine the threshold voltage. In this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a heart rate estimator is added to the above scheme. It reduces the overall system power consumption by reducing the computational burden on the DSP. The complete proposed scheme consists of (i) an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage, hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis. The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V supply. The functionality of each of the individual blocks are successfully validated using postextraction process corner simulations and through real ECG test signals taken from the PhysioNet database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the measurement results are discussed here. The analog classification scheme is successfully validated using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac

Millimeter-Scale and Energy-Efficient RF Wireless System

This dissertation focuses on energy-efficient RF wireless system with millimeter-scale dimension, expanding the potential use cases of millimeter-scale computing devices. It is challenging to develop RF wireless system in such constrained space. First, millimeter-sized antennae are electrically-small, resulting in low antenna efficiency. Second, their energy source is very limited due to the small battery and/or energy harvester. Third, it is required to eliminate most or all off-chip devices to further reduce system dimension. In this dissertation, these challenges are explored and analyzed, and new methods are proposed to solve them. Three prototype RF systems were implemented for demonstration and verification. The first prototype is a 10 cubic-mm inductive-coupled radio system that can be implanted through a syringe, aimed at healthcare applications with constrained space. The second prototype is a 3x3x3 mm far-field 915MHz radio system with 20-meter NLOS range in indoor environment. The third prototype is a low-power BLE transmitter using 3.5x3.5 mm planar loop antenna, enabling millimeter-scale sensors to connect with ubiquitous IoT BLE-compliant devices. The work presented in this dissertation improves use cases of millimeter-scale computers by presenting new methods for improving energy efficiency of wireless radio system with extremely small dimensions. The impact is significant in the age of IoT when everything will be connected in daily life.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147686/1/yaoshi_1.pd