Characterization and Design Methodologies for Wearable Passive UHF RFID Tag Antennas for Wireless Body-Centric Systems

Radio Frequency Identification (RFID) is a wireless automatic identification technology that utilizes electrically active tags – low-cost and low-power wireless communication devices that let themselves transparently and unobstructively be embedded into everyday objects to remotely track information of the object’s physical location, origin, and ownership. At ultra-high frequencies (UHF), this technology uses propagating electromagnetic waves for communication, which enables the fast identification of tags at large distances. A passive RFID tag includes two main components; a tag antenna and an RFID integrate circuit (tag IC). A passive tag relies solely on the external power harvested from an incident electromagnetic wave to run its circuitry and for data transmission. The passiveness makes the tag maintenance-free, simple, and low-cost, allowing large-scale commercial applications in the supply chain, ticketing, and asset tracking. The future of RFID, however, lies in the transition from traditional embedded applications to wearable intelligent systems, in which the tags are seamlessly integrated with everyday clothing. Augmented with various ambient and biochemical sensors, the tag is capable of detecting physical parameters of its environment and providing continuous monitoring of human vital signs. Tremendous amount of tagged entities establish an intelligent infrastructure that is personalized and tailored to the needs of each individual and ultimately, it recedes into the background of our daily life. Although wearable tags in intelligent systems have the enormous potential to revolutionize the quality of human life, the emerging wearable RFID applications introduce new challenges for designers developing efficient and sophisticated RFID systems. Traditional tag design parameters and solutions will no longer respond to the new requirements. Instead, the whole RF community must adopt new methods and unconventional approaches to achieve advanced wearable tags that are highly transparently integrated into our daily life. In this research work, an empirical as well as a theoretical approach is taken to address the above-mentioned wearable RFID tag challenges. Exploiting new analysis tools in combination with computational electromagnetics, a novel technique to model the human body in UHF applications for initiating the design of optimized wearable tags is developed. Further, fundamental unprecedented UHF characteristics of advanced wearable electronics materials – electro-textiles, are established. As an extremely important outcome of this research work, innovative optimization methodologies for the promotion of novel and advanced wearable UHF antennas are proposed. Particularly, it is evidenced that proper embroidery fabrication techniques have the great potential to realize wearable tag antennas exhibiting excellent RF performance and structural properties for the seamless integration with clothing. The kernel of this research work is the realization of a flexible and fully embroidered passive UHF RFID patch tag prototype achieving optimized performance in close vicinity of the high-permittivity and dissipative human body. Its performance may be considered as a benchmark for future wearable antenna designs. This shows that this research work outcome forms an important contribution to the state of the art and a milestone in the development towards wearable intelligence

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Control and Stability of Residential Microgrid with Grid-Forming Prosumers

The rise of the prosumers (producers-consumers), residential customers equipped with behind-the-meter distributed energy resources (DER), such as battery storage and rooftop solar PV, offers an opportunity to use prosumer-owned DER innovatively. The thesis rests on the premise that prosumers equipped with grid-forming inverters can not only provide inertia to improve the frequency performance of the bulk grid but also support islanded operation of residential microgrids (low-voltage distribution feeder operated in an islanded mode), which can improve distribution grids’ resilience and reliability without purposely designing low-voltage (LV) distribution feeders as microgrids. Today, grid-following control is predominantly used to control prosumer DER, by which the prosumers behave as controlled current sources. These grid-following prosumers deliver active and reactive power by staying synchronized with the existing grid. However, they cannot operate if disconnected from the main grid due to the lack of voltage reference. This gives rise to the increasing interest in the use of grid-forming power converters, by which the prosumers behave as voltage sources. Grid-forming converters regulate their output voltage according to the reference of their own and exhibit load sharing with other prosumers even in islanded operation. Making use of grid-forming prosumers opens up opportunities to improve distribution grids’ resilience and enhance the genuine inertia of highly renewable-penetrated power systems. Firstly, electricity networks in many regional communities are prone to frequent power outages. Instead of purposely designing the community as a microgrid with dedicated grid-forming equipment, the LV feeder can be turned into a residential microgrid with multiple paralleled grid-forming prosumers. In this case, the LV feeder can operate in both grid-connected and islanded modes. Secondly, gridforming prosumers in the residential microgrid behave as voltage sources that respond naturally to the varying loads in the system. This is much like synchronous machines extracting kinetic energy from rotating masses. “Genuine” system inertia is thus enhanced, which is fundamentally different from the “emulated” inertia by fast frequency response (FFR) from grid-following converters. Against this backdrop, this thesis mainly focuses on two aspects. The first is the small-signal stability of such residential microgrids. In particular, the impact of the increasing number of grid-forming prosumers is studied based on the linearised model. The impact of the various dynamic response of primary sources is also investigated. The second is the control of the grid-forming prosumers aiming to provide sufficient inertia for the system. The control is focused on both the inverters and the DC-stage converters. Specifically, the thesis proposes an advanced controller for the DC-stage converters based on active disturbance rejection control (ADRC), which observes and rejects the “total disturbance” of the system, thereby enhancing the inertial response provided by prosumer DER. In addition, to make better use of the energy from prosumer-owned DER, an adaptive droop controller based on a piecewise power function is proposed, which ensures that residential ESS provide little power in the steady state while supplying sufficient power to cater for the demand variation during the transient state. Proposed strategies are verified by time-domain simulations

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Physical Aspects of VLSI Design with a Focus on Three-Dimensional Integrated Circuit Applications

This work is on three-dimensional integration (3DI), and physical problems and aspects of VLSI design. Miniaturization and highly complex integrated systems in microelectronics have led to the 3DI development as a promising technological approach. 3DI offers numerous advantages: Size, power consumption, hybrid integration etc., with more thermal problems and physical complexity as trade-offs. We open this work by presenting the design and testing of an example 3DI system, to our knowledge the first self-powering system in a three-dimensional SOI technology. The system uses ambient optical energy harvested by a photodiode array and stored in an integrated capacitor. An on-chip metal interconnect network, beyond its designed role, behaves as a parasitic load vulnerable to electromagnetic coupling. We have developed a spatially-dependent, transient Green's Function based method of calculating the response of an interconnect network to noise. This efficient method can model network delays and noise sensitivity, which are involved problems in both planar and especially in 3DICs. Three-dimensional systems are more susceptible to thermal problems, which also affect VLSI with high power densities, of complex systems and under extreme temperatures. We analytically and experimentally investigate thermal effects in ICs. We study the effects of non-uniform, non-isotropic thermal conductivity of the typically complex IC material system, with a simulator we developed including this complexity. Through our simulations, verified by experiments, we propose a method of cooling or directionally heating IC regions. 3DICs are suited for developing wireless sensor networks, commonly referred to as ``smart dust.'' The ideal smart dust node includes RF communication circuits with on-chip passive components. We present an experimental study of on-chip inductors and transformers as integrated passives. We also demonstrate the performance improvement in 3DI with its lower capacitive loads. 3DI technology is just one example of the intense development in today's electronics, which maintains the need for educational methods to assist student recruitment into technology, to prepare students for a demanding technological landscape, and to raise societal awareness of technology. We conclude this work by presenting three electrical engineering curricula we designed and implemented, targeting these needs among others

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Characterization of embroidered dipole-type RFID tag antennas

Radio Frequency Identification (RFID) is a technology which is used for automatic identification of objects. A typical RFID system consists of a stationary radio-scanner unit, called reader, and a movable transponder, called tag, which is attached to an object. The tags include an antenna and a microchip with internal read/write memory. Tag antenna plays an important role in the overall RFID system performance factors, such as the read range, and the compatibility with tagged objects. This thesis focuses on garment-integrated embroidered tags which can be used for the means of human monitoring and identification. The embroidered tag antennas are sewed on fabric using conductive threads and computer aided sewing machine. Modeling of embroidered tag antennas is not a straightforward task, because embroidered antennas do not have a distinct conductivity, which could be used in the simulation model of them. In fact, conductivity of sewed flat conductive layer depends on the selection of the conductive thread, the thread and stitch density and the sewing pattern. The aim of this thesis has been to investigate the effect of these factors on the conductivity, and evaluate conductivity values for the embroidered dipole-type RFID tag antennas. In this project, T-matched dipoles have been sewed on cotton with two different sewing patterns and also with many different stitch densities. The effect of the geometry of the antenna is also investigated by sewing and measuring straight simple dipoles with both sewing patterns. The achieved read range values of the sewed tag antennas have been up to 7.5 m. In this thesis it is proved that each sewing pattern has its own conductivity and con-ductivity of a sewing pattern improves if the pattern consists of sewed lines along the direction of current flow. It is not necessary to sew the antenna with a high thread and stitch density. We can achieve high conductivities even from very sparsely sewed an-tennas, using less conductive threads and spending considerably less time on sewing. The evaluated conductivities and the presented simulation model of the sewed dipoles in this project can be used in future for optimization of the sewed antennas to operate in the vicinity of body

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized