Dual-band FSK receiver and building block design for UWB impulse radio

Master'sMASTER OF ENGINEERIN

Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 173-183).Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures designed for energy constrained wireless applications. First, as a case study, a highly digital, voltage scalable flash ADC is presented. The flash ADC, implemented in 0.18 [mu]m CMOS, leverages redundancy and calibration to achieve robust operation at supply voltages from 0.2 V to 0.9 V. Next, the thesis expands in scope to describe a pulsed, noncoherent ultra-wideband transceiver chipset, implemented in 90 nm CMOS and operating in the 3-to-5 GHz band. The all-digital transmitter employs capacitive combining and pulse shaping in the power amplifier to meet the FCC spectral mask without any off-chip filters. The noncoherent receiver system-on-chip achieves both energy efficiency and high performance by employing simple amplifier and ADC structures combined with extensive digital calibration. Finally, the transceiver chipset is integrated in a complete system for wireless insect flight control.(cont.) Through the use of a flexible PCB and 3D die stacking, the total weight of the electronics is kept to 1 g, within the carrying capacity of an adult Manduca sexta moth. Preliminary wireless flight control of a moth in a wind tunnel is demonstrated.Ph.D

Design of a correlator for UWB transceivers

Master'sMASTER OF ENGINEERIN

Design of low power CMOS UWB transceiver ICs

Master'sMASTER OF ENGINEERIN

Nested chopper stabilization in analog multipliers and mixers

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 97-99).We describe a general offset-cancelling architecture for analog multiplication using chopper stabilization. Chopping is used to modulate the offset away the output signal where it can be easily filtered out, providing continuous offset reduction which is insensitive to drift. Both square wave chopping and chopping with orthogonal spreading codes are tested and shown to reduce the offset down to the microvolt level. In addition, we apply the nested chopping technique to an analog multiplier which employs two levels of chopping to reduce the offset even further. We discuss the limits on the performance of the various chopping methods in detail, and present a detailed analysis of the residual offset due to charge injection spikes. An illustrative CMOS prototype of a chopper-stabilized general-purpose multiplier in a 0.18/pm process is presented which achieves a worst-case offset of 1.5/tV. This is the lowest measured offset reported in the DC analog multiplier literature by a margin of two orders of magnitude. The prototype multiplier is also tested with AC inputs as a squarer, variable gain amplifier, and direct-conversion mixer, demonstrating that chopper stabilization is effective for both DC and AC multiplication. The AC measurements show that chopping removes not only offset, but also 1/f noise and 2nd-order harmonic distortion. The specific application of chopper stabilization to RF direct-conversion mixers is also discussed in detail, showing how it can be used to improve the sensitivity of direct-conversion receivers by reducing the mixer's offset, 1/f noise, and even-order distortion. A prototype IC of a chopper-stabilized RF mixer in a 0.18pm CMOS process is presented, along with measured results.by Philip Godoy.S.M

Wide Range High Precision CMOS Exponential Circuit Based on Linear Least Squares Approach

A new strategy to implement exponential circuit in CMOS technology is presented in this paper. The proposed method is based on the new approximation function optimized by linear least squares approach to extend the output dynamic range. The current mode method is employed for realization of circuits, because of simple circuitry and intuitive topology. Unlike to the some reported circuits which were designed in the subthreshold region, the proposed design operates in the saturation region which provides acceptable bandwidth for the circuit. In order to validate the circuit performance, the post layout simulation results are presented using HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology. The results demonstrate 78 dB output dynamic range with the linearity error less than ±0.5 dB which shows a remarkable improvement in comparison with previously reported works. A bandwidth of 67 MHz, maximum power consumption of 0.326 mW under supply voltage of 1.5 V, and 0.77% error for temperature variations are further achievement of the design