Fault Tolerant DC–DC Converters at Homes and Offices

The emergence of direct current (DC) microgrids within the context of residential buildings and offices brings in a whole new paradigm in energy distribution. As a result, a set of technical challenges arise, concerning the adoption of efficient, cost-effective, and reliable DC-compatible power conditioning solutions, suitable to interface DC microgrids and energy consuming elements. This thesis encompasses the development of DC–DC power conversion solutions, featuring improved availability and efficiency, suitable to meet the requirements of a comprehensive set of end-uses commonly found in homes and offices. Based on the energy consumption profiles and requirements of the typical elements found at homes and offices, three distinctive groups are established: light-emitting diode (LED) lighting, electric vehicle (EV) charging, and general appliances. For each group, a careful evaluation of the criteria to fulfil is performed, based on which at least one DC–DC power converter is selected and investigated. Totally, a set of five DC–DC converter topologies are addressed in this work, being specific aspects related to fault diagnosis and/or fault tolerance analysed with particular detail in two of them. Firstly, mathematical models are described for LED devices and EV batteries, for the development of a theoretical analysis of the systems’ operation through computational simulations. Based on a compilation of requirements to account for in each end-use (LED lighting, EV charging, and general appliances), brief design considerations are drawn for each converter topology, regarding their architecture and control strategy. Aiming a detailed understanding of the two DC–DC power conversion systems subjected to thorough evaluation in this work – interleaved boost converter and fault-tolerant single-inductor multiple-output (SIMO) converter – under both normal and abnormal conditions, the operation of the systems is evaluated in the presence of open-circuit (OC) faults. Parameters of interest are monitored and evaluated to understand how the failures impact the operation of the entire system. At this stage, valuable information is obtained for the development of fault diagnosis strategies. Taking profit of the data collected in the analysis, a novel fault diagnostic strategy is presented, targeting interleaved DC–DC boost converters for general appliances. Ease of implementation, fast diagnostic and robustness against false alarms distinguish the proposed approach over the state-of-the-art. Its effectiveness is confirmed through a set of operation scenarios, implemented in both simulation environment and experimental context. Finally, an extensive set of reconfiguration strategies is presented and evaluated, aiming to grant fault tolerance capability to the multiple DC–DC converter topologies under analysis. A hybrid reconfiguration approach is developed for the interleaved boost converter. It is demonstrated that the combination of reconfiguration strategies promotes remarkable improvements on the post-fault operation of the converter. In addition, an alternative SIMO converter architecture, featuring inherent tolerance against OC faults, is presented and described. To exploit the OC fault tolerance capability of the fault-tolerant SIMO converter, a converter topology targeted at residential LED lighting systems, two alternative reconfiguration strategies are presented and evaluated in detail. Results obtained from computational simulations and experimental tests confirm the effectiveness of the approaches. To further improve the fault-tolerant SIMO converter with regards to its robustness against sensor faults, while simplifying its hardware architecture, a sensorless current control strategy is presented. The proposed control strategy is evaluated resorting to computational simulations.O surgimento de micro-redes em corrente contínua (CC) em edifícios residenciais e de escritórios estabelece um novo paradigma no domínio da distribuição de energia. Como consequência disso, surge uma panóplia de desafios técnicos ligados à adopção de soluções de conversão de energia, compatíveis com CC, que demonstrem ser eficientes, rentáveis e fiáveis, capazes de estabelecer a interface entre micro-redes em CC e as cargas alimentadas por esse sistema de energia. Até aos dias de hoje, os conversores CC–CC têm vindo a ser maioritariamente utilizados em aplicações de nicho, que geralmente envolvem níveis de potência reduzidos. Porém, as perspectivas futuras apontam para a adopção, em larga escala, destas tecnologias de conversão de energia, também em equipamentos eléctricos residenciais e de escritórios. Tal como qualquer outra tecnologia de conversão electrónica de potência, os conversores CC–CC podem ver o seu funcionamento afectado por falhas que degradam o seu bom funcionamento, sendo que essas falhas acabam por afectar não apenas os conversores em si, mas também as cargas que alimentam, limitando assim o tempo de vida útil do conjunto conversor + carga. Desta forma, é fulcral localizar a origem da falha, para que possam ser adoptadas acções correctivas, capazes de limitar as consequências nefastas associadas à falha. Para responder a este desafio, esta tese contempla o desenvolvimento de soluções de conversão de energia CC–CC altamente eficientes e fiáveis, capazes de responder a requisitos impostos por um conjunto alargado de equipamentos frequentemente encontrados em habitações e escritórios. Com base nos perfis de consumo de energia eléctrica e nos requisitos impostos pelas cargas tipicamente utilizadas em habitações e escritórios, são estabelecidos três grupos distintos: iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral. Para cada grupo, é efectuada uma avaliação cuidadosa dos critérios a respeitar, sendo com base nesses critérios que será escolhida e investigada pelo menos uma topologia de conversor CC–CC. No total, são abordadas cinco topologias de conversores CC–CC distintas, sendo que os aspectos ligados ao diagnóstico de avarias e/ou tolerância a falhas são analisados com particular detalhe em duas dessas topologias. Inicialmente, são estabelecidos modelos matemáticos descritivos do comportamento das principais cargas consideradas no estudo – díodos emissores de luz e baterias de VEs – visando a análise teórica do funcionamento dos sistemas em estudo, suportada por simulações computacionais. Com base numa compilação de requisitos a ter em conta em cada aplicação – iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral – são estabelecidas considerações ligadas à escolha de cada topologia de conversor não isolado, no que respeita à sua arquitectura e estratégia de controlo. Visando o conhecimento aprofundado das duas topologias de conversor CC–CC alvo de particular enfoque neste trabalho – conversor entrelaçado elevador e conversor de entrada única e múltiplas saídas, tolerante a falhas – quer em funcionamento normal, quer em funcionamento em modo de falha, é avaliado o funcionamento de ambas as topologias na presença de falhas de circuito aberto nos semicondutores activos. Para o efeito, são monitorizados e analisados parâmetros úteis à percepção da forma como os modos de falha avaliados neste trabalho impactam o funcionamento de todo o sistema. Nesta fase, é obtida informação fundamental ao desenvolvimento de estratégias de diagnóstico de avarias, particularmente indicadas para avarias de circuito aberto nos semicondutores activos dos conversores em estudo. Com base na informação recolhida anteriormente, é apresentada uma nova estratégia de diagnóstico de avarias direccionada a conversores CC–CC elevadores entrelaçados utilizados em aparelhos eléctricos, em geral. Facilidade de implementação, rapidez e robustez contra falsos positivos são algumas das características que distinguem a estratégia proposta em relação ao estado da arte. A sua efectividade é confirmada com recurso a uma multiplicidade de cenários de funcionamento, implementados quer em ambiente de simulação, quer em contexto experimental. Por fim, é apresentada e avaliada uma gama alargada de estratégias de reconfiguração, que visam assegurar a tolerância a falhas das diversas topologias de conversores CC–CC em estudo. É desenvolvida uma estratégia de reconfiguração híbrida, direccionada ao conversor entrelaçado elevador, que combina múltiplas medidas de reconfiguração mais simples num único procedimento. Demonstra-se que a combinação de múltiplas estratégias de reconfiguração introduz melhorias substanciais no funcionamento do conversor ao longo do período pós-falha, ao mesmo tempo que assegura a manutenção da qualidade da energia à entrada e saída do conversor reconfigurado. Noutra frente, é apresentada e descrita uma arquitectura alternativa do conversor de entrada única e múltiplas saídas, com tolerância a falhas de circuito aberto. Através da configuração proposta, é possível manter o fornecimento de energia eléctrica a todas as saídas do conversor. Para tirar máximo proveito da tolerância a falhas do conversor de entrada única e múltiplas saídas, uma topologia de conversor indicada para sistemas residenciais de iluminação baseados em díodos emissores de luz, são apresentadas e avaliadas duas estratégias de reconfiguração do conversor, exclusivamente baseadas na adaptação do controlo aplicado ao conversor. Os resultados de simulação computacional e os resultados experimentais obtidos confirmam a efectividade das abordagens adoptadas, através da melhoria da qualidade da energia eléctrica fornecida às diversas saídas do conversor. São assim asseguradas condições essenciais ao funcionamento ininterrupto e estável dos sistemas de iluminação, já que a qualidade da energia eléctrica fornecida aos sistemas de iluminação tem impacto directo na qualidade da luz produzida. Por fim, e para aprimorar o conversor de entrada única e múltiplas saídas tolerante a falhas, no que respeita à sua robustez contra falhas em sensores, é apresentada uma estratégia de controlo de corrente que evita o recurso excessivo a sensores e, ao mesmo tempo, simplifica a estrutura de controlo do conversor. A estratégia apresentada é avaliada através de simulações computacionais. A abordagem apresentada assume vantagens em múltiplos domínios, sendo de destacar vantagens como a melhoria da fiabilidade de todo o sistema de iluminação (conversor + carga), os ganhos atingidos ao nível do rendimento, a redução do custo de implementação da solução, ou a simplificação da estrutura de controlo.This work was supported by the Portuguese Foundation for Science and Technology (FCT) under grant number SFRH/BD/131002/2017, co-funded by the Ministry of Science, Technology and Higher Education (MCTES), by the European Social Fund (FSE) through the ‘Programa Operacional Regional Centro’ (POR-Centro), and by the Human Capital Operational Programme (POCH)

A Single-Stage LED Driver Based on ZCDS Class-E Current-Driven Rectifier as a PFC for Street-Lighting Applications

This paper presents a light-emitting diode (LED) driver for street-lighting applications that uses a resonant rectifier as a power-factor corrector (PFC). The PFC semistage is based on a zero-current and zero-derivative-switching (ZCDS) Class-E current-driven rectifier, and the LED driver semistage is based on a zero-voltage-switching (ZVS) Class-D LLC resonant converter that is integrated into a single-stage topology. To increase the conduction angle of the bridge-rectifier diodes current and to decrease the current harmonics that are injected in the utility line, the ZCDS Class-E rectifier is placed between the bridge-rectifier and a dc-link capacitor. The ZCDS Class-E rectifieris driven by a high-frequency current source, which is obtained from a square-wave output voltage of the ZVS Class-D LLC resonant converter using a matching network. Additionally, the proposed converter has a soft-switching characteristic that reduces switching losses and switching noise. A prototype for a 150-W LED street light has been developed and tested to evaluate the performance of the proposed approach. The proposed LED driver had a high efficiency (>91%), a high PF (>0.99), and a low total harmonic distortion (THD i <; 8%) under variation of the utility-line input voltage from 180 to 250 V rms . These experimental results demonstrate the feasibility of the proposed LED scheme

Bridgeless SEPIC Converter Based Computer Power Supply Using Coupled Inductor

Switched Mode Power Supplies (SMPS) are used as power source for computers. Conventional SMPS used in computers are suffered by some serious problems such as poor power quality, high device stress, slow dynamic response, high harmonic contents, periodically dense, peak currents, distorted input current. To minimize these problems, a non-isolated bridgeless buck-boost single ended primary inductance converter (SEPIC) using coupled inductor is introduced at the front end of the SMPS, which is operated in discontinuous conduction mode (DCM). This proposed technique reduces the Total Harmonic Distortion(THD), which results in power factor improvement. The DC output voltage of the SMPS is almost a constant voltage which is regulated by means of the proposed SEPIC converter. For obtaining different dc voltage levels for the PC applications, the output of the front end SEPIC converter is fed to the half-bridge DC-DC converter. The output voltages of the SMPS are controlled by controlling any one of the output voltages. Design and simulation of the proposed converter are carried out using the MATLAB/simulink software

Comparison of Current Balancing Configurations for Primary Parallel Isolated Boost Converter

Different current balancing configurations have been investigated for Primary Parallel Isolated Boost Converter (PPIBC). It has been shown that parallel branch current balancing is possible with several configurations of coupled/uncoupled inductors. Analytical expressions for branch currents have been derived for different cases of gate signal mismatch causing current imbalance. It has been observed that turn-on and turn-off delays in parallel power stages of the PPIBC have different effects in the branch currents deviating from ideal. It has also been observed that in some configurations inductance differences due to core tolerances play an important role in current imbalance. Analytical and simulation results have shown that another side effect of the gate signal delay and inductor value difference is additional voltage stress over the switches during the mismatch times. Advantages of each configuration in terms of effective current balancing, efficiency and manufacturing simplicity have been highlighted. Simulations with ideal components for each case have been carried out to confirm the analytical derivations. Experimental results have also been included to show the performances of different configurations where component non-idealities like transformer leakage inductances also become effective

Novel Offline Switched Mode Power Supplies for Solid State Lighting Applications

In recent years, high brightness light emitting diodes (HBLEDs) have increasingly attracted the interest of both industrial manufacturers and academic research community. Among the several aspects that make LED technology so attractive, the most appreciated characteristics are related to their robustness, high efficiency, small size, easy dimming capability, long lifetime, very short switch-on/switch-off times and mercury free manufacturing. Even if all such qualities would seem to give to solid state lighting a clear advantage over all the other kinds of competing technologies, the issues deriving from the need of LED technology improvement, on one hand, and of the development of suitable electronic ballasts to properly drive such solid state light sources, on the other, have so far hindered the expected practical applications. The latter problem, in particular, is nowadays considered the main bottleneck in view of a widespread diffusion of solid state technology in the general lighting market, as a suitable replacement of the still dominant solutions, namely halogen and fluorescent lamps. In fact, if it is true that some aspects of the devices’ technology (e.g. temperature dependent performance, light quality, efficiency droop, high price per lumen, etc…) still need further improvements, it is now generally recognized that one of the key requirements, for a large scale spread of solid state lighting, is the optimization of the driver. In particular, the most important specifications for a LED lamp ballast are: high reliability and efficiency, high power factor, output current regulation, dimming capability, low cost and volume minimization (especially in domestic general lighting applications). From this standpoint, the main goal is, therefore, to find out simple switched mode power converter topologies, characterized by reduced component count and low current/voltage stresses, that avoid the use of short lifetime devices like electrolytic capacitors. Moreover, if compactness is a major issue, also soft switching capability becomes mandatory, in order to enable volume minimization of the reactive components by increasing the switching frequency in the range of the hundreds of kHz without significantly affecting converter’s efficiency. It is worth mentioning that, in order to optimize HBLED operation, also other matters, like the lamp thermal management concern, should be properly addressed in order to minimize the stress suffered by the light emitting devices and, consequently, the deterioration of the light quality and of the expected lamp lifetime. However, being this work focused on the issues related to the research of innovative driving solutions, the aforementioned thermal management problems, as also all the topics related to the improvement of solid state devices’ technology, will be left aside. The main goal of the work presented in this thesis is, indeed, to find out, analyze and optimize new suitable topologies, capable of matching the previously described specifications and also of successfully facing the many challenges dictated by the future of general lighting. First of all, a general overview of solid state lighting features, of the state of the art of lighting market and of the main LED driving issues will be provided. After this first introduction, the offline driving concern will be extensively discussed and different ways of approaching the problem, depending on the specific application considered, will be described. The first kind of approach investigated is based on the use of a simple structure relying on a single power conversion stage, capable of concurrently ensuring: compliance with the standards limiting the input current harmonics, regulation of the load current and also galvanic isolation. The constraints deriving from the need to fulfil the EN 61000-3-2 harmonics standard requirements, when using such kind of solution for low power (<15W) LED driving purposes, will be extensively discussed. A low cost, low component count, high switching frequency converter, based on the asymmetrical half bridge flyback topology, has been studied, developed and optimized. The simplicity and high compactness, characterizing this solution, make it a very good option for CFL and bulb replacement applications, in which volume minimization is mandatory in order to reach the goal of placing the whole driving circuitry in the standard E27 sockets. The analysis performed will be presented, together with the design procedure, the simulation outcomes and the different control and optimization techniques that were studied, implemented and tested on the converter's laboratory prototype. Another interesting approach, that will be considered, is based on the use of integrated topologies in which two different power conversion stages are merged by sharing the same power switch and control circuitry. In the resulting converter, power factor correction and LED current regulation are thus performed by two combined semi-stages in which both the input power and the output current have to be managed by the same shared switch. Compared with a conventional two-stages configuration, lower circuit complexity and cost, reduced component count and higher compactness can be achieved through integration, at cost of increased stress levels on the power switch and of losing a degree of freedom in converter design. Galvanic isolation can be provided or not depending on the topologies selected for integration. If non-isolated topologies are considered for both semi-stages, the user safety has to be guaranteed by assuring mechanical isolation throughout the LED lamp case. The issue, deriving from the need of smoothing the pulsating power absorbed from the line while avoiding the use of short lifetime electrolytic capacitors, will be addressed. A set of integrated topologies, used as HBLED lamp power supplies, will be investigated and a generalized analysis will be presented. Their input line voltage ripple attenuation capability will be examined and a general design procedure will be described. Moreover, a novel integrated solution, based on the use of a double buck converter, for an about 15W rated down-lighting application will be presented. The analysis performed, together with converter design and power factor correction concerns will be carefully discussed and the main outcomes of the tests performed at simulation level will be provided. The last kind of approach to be discussed is based on a multi-stage structure that results to be a suitable option for medium power applications, like street lighting, in which compactness is not a major concern. By adopting such kind of solution it is, indeed, possible to optimize converter’s behavior both on line and on load side, thereby guaranteeing both an effective power factor correction at the input and proper current regulation and dimming capability at the output. Galvanic isolation can be provided either by the input or the output stage, resulting in a standard two stage configuration, or by an additional intermediate isolated DC-DC stage (operating in open loop with a constant input/output voltage conversion ratio) that namely turns the AC/DC converter topology into a three stage configuration. The efficiency issue, deriving from the need of multiple energy processing along the path between the utility grid and the LED load, can be effectively addressed thanks to the high flexibility guaranteed by this structure that, relaxing the design constraint, allows to easily optimize each stage. A 150W nominal power rated ballast for street solid state lighting applications, based on the latter (three stage) topology, has been investigated. The analysis performed, the design procedure and the simulations outcomes will be carefully described, as well as the experimental results of the tests made on the implemented laboratory prototype

A Control Scheme for an AC-DC Single-Stage Buck-Boost PFC Converter with Improved Output Ripple Reduction

AC-DC power factor correction (PFC) single-stage converters are attractive because of their cost and their simplicity. In these converters, both PFC and power conversion are done at the same time using a single converter that regulates the output. Since they have only a single controller, these converters operate with an intermediate transformer primary-side DC bus voltage that is unregulated and is dependent on the converters’ operating conditions and component values. This means that the DC bus voltage can vary significantly as line and load conditions are changed. Such a variable DC bus voltage makes it difficult to optimally design the converter transformer as well as the DC bus capacitor. One previously proposed single-stage AC-DC converter, the Single-Stage Buck-Boost Direct Energy Transfer (SSBBDET) converter has a clamping mechanism that can clamp the DC bus voltage to a pre-set limit. The clamping mechanism, however, superimposes a low frequency 120 Hz AC component on the output DC voltage so that some means must be taken to reduce this component. These means, however, make the converter transient slow and sluggish. The main objective of this thesis is to minimize the 120 Hz output ripple component and to improve the dynamic response of the SSBBDET converter by using a new control scheme. In the thesis, the operation of the SSBBDET converter is reviewed and the proposed control method is introduced and explained in detail. Key design considerations for the design of the converter controller are discussed and the converter’s ability to operate with fixed DC bus voltage, low output ripple and fast dynamic response is confirmed with experimental results obtained from a prototype converter

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

High power density AC to DC conversion with reduced input current harmonics

PhD ThesisThis thesis investigates the bene ts and challenges arising from the use of minimal capacitance in AC to DC converters. The purpose of the research is to ultimately improve the power density and power factor of electrical systems connected to the grid. This is carried out in the con- text of a low cost brushless DC drive system operating from an o ine power supply. The work begins with a review of existing applications where it is prac- tical to use a limited amount of DC link capacitance. The vast majority of these have a load which is insensitive to supply power variations at twice the line frequency. Low performance motor drives are found to be the most prevalent, with the inertia of the rotor mitigating the e ect of torque ripple. Further research is carried out on active power factor cor- rection techniques suitable for this application, leading to the conclusion that no appropriate systems exist. A power supply is developed to enable a 24V, 200W brushless motor drive to operate from the mains. The system runs successfully using only 1µF of DC link capacitance, which causes the motor supply volt- age to have 100% ripple. It is noted that whilst this drastically reduces the low frequency input current harmonics, those occurring at the load switching frequency are greatly increased. To combat this, a novel active power factor correction system is proposed using a notch lter to detect the input current error. The common problem of voltage feedback ripple is avoided by eliminating the voltage control loop altogether. The main limitations are identi ed as a high sensitivity to load step changes and variations in line frequency. Despite this, a high power factor is maintained in all operating conditions, as well as compliance with the relevant harmonic standards.Dyson Technology Ltd and Newcastle Univer- sit