Control techniques for thermal-aware energy-efficient real time multiprocessor scheduling

La utilización de microprocesadores multinúcleo no sólo es atractiva para la industria sino que en muchos ámbitos es la única opción. La planificación tiempo real sobre estas plataformas es mucho más compleja que sobre monoprocesadores y en general empeoran el problema de sobre-diseño, llevando a la utilización de muchos más procesadores /núcleos de los necesarios. Se han propuesto algoritmos basados en planificación fluida que optimizan la utilización de los procesadores, pero hasta el momento presentan en general inconvenientes que los alejan de su aplicación práctica, no siendo el menor el elevado número de cambios de contexto y migraciones.Esta tesis parte de la hipótesis de que es posible diseñar algoritmos basados en planificación fluida, que optimizan la utilización de los procesadores, cumpliendo restricciones temporales, térmicas y energéticas, con un bajo número de cambios de contexto y migraciones, y compatibles tanto con la generación fuera de línea de ejecutivos cíclicos atractivos para la industria, como de planificadores que integran técnicas de control en tiempo de ejecución que permiten la gestión eficiente tanto de tareas aperiódicas como de desviaciones paramétricas o pequeñas perturbaciones.A este respecto, esta tesis contribuye con varias soluciones. En primer lugar, mejora una metodología de modelo que representa todas las dimensiones del problema bajo un único formalismo (Redes de Petri Continuas Temporizadas). En segundo lugar, propone un método de generación de un ejecutivo cíclico, calculado en ciclos de procesador, para un conjunto de tareas tiempo real duro sobre multiprocesadores que optimiza la utilización de los núcleos de procesamiento respetando también restricciones térmicas y de energía, sobre la base de una planificación fluida. Considerar la sobrecarga derivada del número de cambios de contexto y migraciones en un ejecutivo cíclico plantea un dilema de causalidad: el número de cambios de contexto (y en consecuencia su sobrecarga) no se conoce hasta generar el ejecutivo cíclico, pero dicho número no se puede minimizar hasta que se ha calculado. La tesis propone una solución a este dilema mediante un método iterativo de convergencia demostrada que logra minimizar la sobrecarga mencionada.En definitiva, la tesis consigue explotar la idea de planificación fluida para maximizar la utilización (donde maximizar la utilización es un gran problema en la industria) generando un sencillo ejecutivo cíclico de mínima sobrecarga (ya que la sobrecarga implica un gran problema de los planificadores basados en planificación fluida).Finalmente, se propone un método para utilizar las referencias de la planificación fuera de línea establecida en el ejecutivo cíclico para su seguimiento por parte de un controlador de frecuencia en línea, de modo que se pueden afrontar pequeñas perturbaciones y variaciones paramétricas, integrando la gestión de tareas aperiódicas (tiempo real blando) mientras se asegura la integridad de la ejecución del conjunto de tiempo real duro.Estas aportaciones constituyen una novedad en el campo, refrendada por las publicaciones derivadas de este trabajo de tesis.<br /

Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPNs

We present an energy-effcient thermal-aware real-time global scheduler for a set of hard real-time (HRT) tasks running on a multiprocessor system. This global scheduler fulfills the thermal and temporal constraints by handling two independent variables, the task allocation time and the selection of clock frequency. To achieve its goal, the proposed scheduler is split into two stages. An off-line stage, based on a deadline partitioning scheme, computes the cycles that the HRT tasks must run per deadline interval at the minimum clock frequency to save energy while honoring the temporal and thermal constraints, and computes the maximum frequency at which the system can run below the maximum temperature. Then, an on-line, event-driven stage performs global task allocation applying a Fixed-Priority Zero-Laxity policy, reducing the overhead of quantum-based or interval-based global schedulers. The on-line stage embodies an adaptive scheduler that accepts or rejects soft RT aperiodic tasks throttling CPU frequency to the upper lowest available one to minimize power consumption while meeting time and thermal constraints. This approach leverages the best of two worlds: the off-line stage computes an ideal discrete HRT multiprocessor schedule, while the on-line stage manage soft real-time aperiodic tasks with minimum power consumption and maximum CPU utilization

9. Real-Time: Basic Concepts

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Smart real time operating system

Ph.DDOCTOR OF PHILOSOPH

Online scheduling for real-time multitasking on reconfigurable hardware devices

Nowadays the ever increasing algorithmic complexity of embedded applications requires the designers to turn towards heterogeneous and highly integrated systems denoted as SoC (System-on-a-Chip). These architectures may embed CPU-based processors, dedicated datapaths as well as recon gurable units. However, embedded SoCs are submitted to stringent requirements in terms of speed, size, cost, power consumption, throughput, etc. Therefore, new computing paradigms are required to ful l the constraints of the applications and the requirements of the architecture. Recon gurable Computing is a promising paradigm that provides probably the best trade-o between these requirements and constraints. Dynamically recon gurable architectures are their key enabling technology. They enable the hardware to adapt to the application at runtime. However, these architectures raise new challenges in SoC design. For example, on one hand, designing a system that takes advantage of dynamic recon guration is still very time consuming because of the lack of design methodologies and tools. On the other hand, scheduling hardware tasks di ers from classical software tasks scheduling on microprocessor or multiprocessors systems, as it bears a further complicated placement problem. This thesis deals with the problem of scheduling online real-time hardware tasks on Dynamically Recon gurable Hardware Devices (DRHWs). The problem is addressed from two angles : (i) Investigating novel algorithms for online real-time scheduling/placement on DRHWs. (ii) Scheduling/Placement algorithms library for RTOS-driven Design Space Exploration (DSE). Regarding the first point, the thesis proposes two main runtime-aware scheduling and placement techniques and assesses their suitability for online real-time scenarios. The first technique discusses the impact of synthesizing, at design time, several shapes and/or sizes per hardware task (denoted as multi-shape task), in order to ease the online scheduling process. The second technique combines a looking-ahead scheduling approach with a slots-based recon gurable areas management that relies on a 1D placement. The results show that in both techniques, the scheduling and placement quality is improved without signi cantly increasing the algorithm time complexity. Regarding the second point, in the process of designing SoCs embedding recon gurable parts, new design paradigms tend to explore and validate as early as possible, at system level, the architectural design space. Therefore, the RTOS (Real-Time Operating System) services that manage the recon gurable parts of the SoC can be re fined. In such a context, gathering numerous hardware tasks scheduling and placement algorithms of various complexity vs performance trade-o s in a kind of library is required. In this thesis, proposed algorithms in addition to some existing ones are purposely implemented in C++ language, in order to insure the compatibility with any C++/SystemC based SoC design methodology.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Design and implementation of a modular scheduling simulator for aerospace applications

Tese de mestrado em Engenharia Informática, apresentada à Universidade de Lisboa, através da Faculdade de Ciências, 2012Sistemas tempo-real têm de produzir os resultados esperados de cada tarefa atempadamente de acordo com a urgência de cada uma. Desde os anos 70 tentam-se obter formas de coordenar a execução das tarefas para cumprir todos os prazos através de algoritmos de escalonamento. Na sua maioria estes algoritmos apesar de terem requerido um extensivo trabalho por parte de quem os criou são simples de compreender. Um dos mais antigos é o algoritmo “Earliest Deadline First”, que consiste em dar maior prioridade às tarefas mais urgentes. Alguns sistemas devido às suas características particulares obedecem a modelos mais complexos. É o caso dos sistemas aeronáuticos onde é necessário manter o isolamento entre as funcionalidades. As funções são agrupadas logicamente em contentores denominados partições. Para garantir essa separação no domínio do tempo introduz-se um esquema de escalonamento a dois níveis. Um primeiro que determina as janelas temporais a dar a cada partição e um segundo nível onde estão as partições e respectivas funções. Os algoritmos de escalonamento utilizados em cada nível não tem de ser iguais; no segundo nível, cada partição pode usar um algoritmo diferente. Após estudar o que actualmente existe decidimos orientar o nosso trabalho para partições e escalonamento hierárquico pois é de onde poderemos vir a obter melhores resultados e soluções para sistemas futuros. Fazendo uso de padrões de desenho, bem como características do Java, tais como herança e polimorfismo conseguimos obter uma solução que após implementada permite aos seus utilizadores simularem a execução de um sistema que estes definam. Permite também obter os eventos e com estes mostrar ao utilizador o que o simulador fez em cada momento do sistema podendo estes resultados ser exibidos em formato textual ou fazer uso de outras aplicações de visualização de resultados.Real-time systems are required to produce results from each task in time, according to the urgency of each one. Since the 1970s researchers try to obtain ways to coordinate the execution of tasks to meet all deadline, by using scheduling algorithms. Although the majority of these algorithms required an extensive work from those who created them, they are simple to understand. One of the oldest is the Earliest Deadline First algorithm, which attributes higher priority to the most urgent tasks. Due to their characteristics, some systems obey to more complex models; this is the case of aerospace systems. These systems require full isolation between functionalities. The functions, composed of tasks (processes), are logically grouped into partitions. To ensure separation in the time domain, a two level scheduling scheme is introduced. The first level determinates the time windows to assign to each partition; in the second level, tasks in each partition compete among them for the execution time assigned to the latter. The scheduling algorithms used in each level do not need to be the same; in the second level, each partition may even employ a different algorithm to schedule its tasks. After studying what currently exists we have decided to guide our work to partitions and hierarchical scheduling because it is where we see producing better results and solutions for future systems. Using design patterns as well as Java properties such as inheritance and polymorphism we were able to obtain a solution that after implemented allows users to simulate the execution of a system defined by them. The tool allows obtaining events and showing them to the user and giving feedback, these events represent the basic functionalities of a real-time system, such as, job launch and job deadline miss and others. These results can be shown in textual form or use other applications of results visualization

Exploring coordinated software and hardware support for hardware resource allocation

Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.Postprint (published version

Dual Priority Scheduling Algorithm Used in the nMPRA Microcontrollers – Dynamic Scheduler

This paper is a follow up of an already published paper that described the static scheduler. It deals with a true dynamic scheduling algorithm that is meant to maximize the CPU utilization. The dual priority algorithm is composed of two different scheduling algorithms, earliest deadline first (EDF) and round robin (RR). We have chosen EDF, because it is a dynamic scheduling algorithm, used in real time operating systems, which can be easily implemented in hardware, by improving the nHSE architecture. The new dynamic scheduler algorithm provides a much better CPU utilization, very good switching time for tasks and events within 5 to 8 machine cycles and guarantees that no task will suffer from starvation