Error modeling, self-calibration and design of pipelined analog to digital converters

Typescript (photocopy).As the field of signal processing accelerates toward the use of high performance digital techniques, there is a growing need for increasingly fast and accurate analog to digital converters. Three highly visible examples of this trend originated in the last decade. The advent of the compact disc revolutionized the way high-fidelity audio is stored, reproduced, recorded and processed. Digital communication links, fiber optic cables and in the near future ISDN networks (Integrated Services Digital Network) are steadily replacing major portions of telephone systems. Finally, video-conferencing, multi-media computing and currently emerging high definition television (HDTV) systems rely more and more on real-time digital data compression and image enhancing techniques. All these applications rely on analog to digital conversion. In the field of digital audio, the required conversion accuracy is high, but the conversion speed limited (16 bits, 2 x 20 kHz signal bandwidth). In the field of image processing, the required accuracy is less, but the data conversion speed high (8-10 bits, 5-20MHz bandwidth). New applications keep pushing for increasing conversion rates and simultaneously higher accuracies. This dissertation discusses new analog to digital converter architectures that could accomplish this. As a consequence of the trend towards digital processing, prominent analog designers throughout the world have engaged in very active research on the topic of data conversion. Unfortunately, literature has not always kept up. At the time of this writing, it seemed rather difficult to find detailed fundamental publications about analog to digital converter design. This dissertation represents a modest attempt to remedy this situation. It is hoped that anyone with a back-ground in analog design could go through this work and pick up the fundamentals of converter operation, as well as a number of more advanced design techniques

Stochastic macromodeling for hierarchical uncertainty quantification of nonlinear electronic systems

A hierarchical stochastic macromodeling approach is proposed for the efficient variability analysis of complex nonlinear electronic systems. A combination of the Transfer Function Trajectory and Polynomial Chaos methods is used to generate stochastic macromodels. In order to reduce the computational complexity of the model generation when the number of stochastic variables increases, a hierarchical system decomposition is used. Pertinent numerical results validate the proposed methodology

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

A Pipeline Analog-To-Digital Converter for a Plasma Impedance Probe

Space instrumentation technology is an essential tool for rocket and satellite research, and is expected to become popular in commercial and military operations in fields such as radar, imaging, and communications. These instruments are traditionally implemented on printed circuit boards using discrete general-purpose Analog-to-Digital Converter (ADC) devices and other components. A large circuit board is not convenient for use in micro-satellite deployments, where the total payload volume is limited to roughly one cubic foot. Because micro-satellites represent a fast growing trend in satellite research and development, there is motivation to explore miniaturized custom application-specific integrated circuit (ASIC) designs to reduce the volume and power consumption occupied by instrument electronics. In this thesis, a model of a new Plasma Impedance Probe (PIP) architecture, which utilizes a custom-built ADC along with other analog and digital components, is proposed. The model can be fully integrated to produce a low-power, miniaturized impedance probe

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics

Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter

This work aims to model the effect of the input offset voltage of an operational amplifier on the performance of a high-precision, voltage-mode, resistor-based multiplying digital-to-analog converter (M-DAC). Based on the model, a high precision current buffer is proposed to isolate the resistor ladder from the operational amplifier. A 14-bit M-DAC operating with a ±1V reference of the proposed architecture. Post-layout simulations show that the proposed architecture reduces the offset voltage to an offset error in the DAC transfer function. The maximum DNL is maintained at -0.385 LSB for an input offset voltage of up to 60mV (1024 LSB). The current buffer also introduces an inversion of the output voltage, yielding a non-inverted output. This alleviates the need for an additional high precision op-amp to invert the output voltage

Partial Binary Tree Network (Pbtn): A New Dynamic Element Matching (Dem) Approach To Current Steering Digital Analog Converter (Dac)

DACs are essential operations in many digital system which required high performance data converters. With shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures highly relying on matched components to perform data converters. However, components matched are nearly impossible to fabricate, there are always mismatch errors which caused the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. With this technique, the time averages of the equivalent components at each of the component positions are equal or nearly equal to reduce the effects of component differences in electronic circuits. The drawback of existing works is DAC would suffer from excessive digital hardware complexity. A complicated encoding is usually necessary for conventional DEM encoders which will lead to a lot of switch transitions at the same time and it will bring glitches to the output signal. In this research, a new DEM algorithm is proposed on Current-Steering DACs with Partial Binary Tree Network (PBTN) algorithm to overcome glitches transitions with low complexity. The analysis related to the performance of DAC such as glitch impulse areas, Integral Nonlinearity (INL), Differential Nonlinearity (DNL) and power consumption are shown to be equivalent and have at least 56% hardware efficient implementations compared to exiting DEM algorithm. Simulation results for 3-bit and 4-bit PBTN compared with 3-bit and 4-bit conventional Binary Tree Network (BTN) show that both algorithms are equivalent in performance with DNL and INL errors of +/- 0.2 LSB and the proposed algorithm has even lower power consumption due to small amount of transmission gates used. Simulation results for 8-bit PBTN with 1MSB randomization achieved INL of 1.5385 LSB and DNL 0.2605 LSB with power consumption of 22.2 mW. Besides that, PBTN algorithm provides the flexibility to improve the DAC performance by increasing numbers of randomization implementation on MSB