An IF-sampling switched capacitor complex lowpass sigma delta modulator with high image rejection.

by Cheng Wang-tung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 97-99).Abstracts in English and Chinese.Abstract --- p.i摘要 --- p.iAcknowledgements --- p.iiTable of Contents --- p.iiiList of Figures --- p.viiList of Tables --- p.xiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Objective --- p.4Chapter 1.3 --- Outline --- p.4Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6Chapter 2.3 --- Theory of ΣΔ modulation --- p.6Chapter 2.3.1 --- Quantization noise --- p.7Chapter 2.3.2 --- Oversampling --- p.8Chapter 2.3.3 --- Noise Shaping --- p.9Chapter 2.3.4 --- Performance Parameter --- p.11Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11Chapter 2.3.6 --- Case Study --- p.12Chapter 2.3.6.1 --- Transfer Function --- p.12Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18Chapter 2.5.1 --- Quadrature signal --- p.18Chapter 2.5.2 --- I/Q Modulation --- p.19Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21Chapter 2.6.1 --- High Level Simulation --- p.23Chapter 2.6.2 --- Discussion --- p.26Chapter 2.7 --- Summary --- p.27Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28Chapter 3.2.1 --- Principle of Operation --- p.30Chapter 3.3 --- Justification of the Proposed Idea --- p.35Chapter 3.4 --- Summary --- p.37Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39Chapter 4.1 --- Introduction --- p.39Chapter 4.2 --- Design of ΣΔ Modulator --- p.39Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40Chapter 4.3 --- Design of Operational Amplifier --- p.45Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45Chapter 4.3.2 --- Common Mode feedback --- p.47Chapter 4.3.3 --- Bias Circuit --- p.49Chapter 4.3.4 --- Simulation Results --- p.50Chapter 4.4 --- Design of Comparator --- p.54Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54Chapter 4.4.2 --- Simulation Results --- p.55Chapter 4.5 --- Design of Clock Generator --- p.56Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57Chapter 4.5.2 --- Simulation Results --- p.58Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59Chapter 4.7 --- Simulation Results --- p.61Chapter 4.7.1 --- Proposed Architecture --- p.62Chapter 4.7.2 --- Traditional Architecture --- p.62Chapter 4.8 --- Summary --- p.63Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65Chapter 5.1 --- Introduction --- p.65Chapter 5.2 --- Common-Centroid Structure --- p.65Chapter 5.3 --- Shielding Technique --- p.67Chapter 5.3.1 --- Shielding of device by substrate --- p.67Chapter 5.3.2 --- Floor Planning --- p.68Chapter 5.4 --- Layout of Power Rail --- p.69Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74Chapter 5.6.1 --- Proposed Architecture --- p.75Chapter 5.6.2 --- Traditional Architecture --- p.77Chapter 5.7 --- Summary --- p.79Chapter Chapter 6 --- Measurement Results --- p.81Chapter 6.1 --- Introduction --- p.81Chapter 6.2 --- Considerations of PCB Design --- p.82Chapter 6.3 --- Measurement Setup --- p.83Chapter 6.4 --- Measurement Results --- p.85Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85Chapter 6.5 --- Summary --- p.92Chapter Chapter 7 --- Conclusion --- p.95Chapter 7.1 --- Conclusion --- p.95Chapter 7.2 --- Future Works --- p.96References --- p.97Appendix --- p.100Chapter A.1 --- Publications --- p.100Chapter A.2 --- Schematic of proposed front end --- p.101Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103Chapter A.5 --- Schematic of biasing circuit --- p.104Chapter A.6 --- Schematic of preamplifier in comparator --- p.105Chapter A.7 --- Schematic of latched part in comparator --- p.106Chapter A.8 --- Schematic of the clock generator --- p.10

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Kvadratuuri-sigma-delta-AD-muuntimet: mallintaminen ja signaalinkäsittely

The versatile nature of modern wireless communications and on the other hand the push towards cost-efficiency, have created a demand for flexible radio transceivers. In addition, size and power consumption are critical for mobile solutions, thus setting their own demands for the circuitry. Traditionally in such architectures, the analog-to-digital converter has been seen as a performance bottleneck, limiting the possibilities to harness the full potential of the available digital signal processing techniques and algorithms. Therefore, analog-to-digital conversion based on a quadrature ΣΔ modulator noise shaping has been brought in as a promising possibility. More efficient noise shaping and better suitability for modern receivers applying complex signal processing principles already, compared to real counterpart make the quadrature converter particularly interesting choice. This thesis discusses the main principles of quadrature ΣΔ converter and related signal modeling. In addition to understanding the basic operation, it is crucial to understand the implementation related nonidealities, which can’t be avoided in any true circuit. One of the most important phenomena in this field, concerning the in-phase/quadrature processing in the transceivers, is the nonideal matching of the components on the two rails. Thus, the latter part of the thesis gives a detailed analysis on the mismatch problem in quadrature ΣΔ converters. Thereafter, the analysis is confirmed by computer simulations. Finally, it is shown that the mismatch mentioned above is a real concern, especially under the influence of a mirror frequency blocking signal. This might very well be the case in a wideband radio receiver with reduced analog selectivity. On the other hand, the analysis shows that educated design of the signal transfer function can be efficiently used to mitigate the interference originating from the mirror frequency in case of mismatch in the complex feedback branch of the modulator. In this way, the generated distortion can be reduced without any additional electronics, which would compromise cost-efficiency and other demands. Additionally, it is pointed out that independent frequency domain mirroring of the noise and the signal component sets challenges for traditional compensation algorithms. Thus, there is a call for innovative ideas to mitigate the mirror frequency distortion in quadrature ΣΔ modulators via digital signal processing. In this way the cost-efficiency, power consumption and size requirements wouldn’t be jeopardized due to additional electronics. /Kir10Nykyaikaisen langattoman tiedonsiirron monimuotoisuus, ja toisaalta tarve kustannustehokkuuteen, ovat luoneet tarpeen joustaville radiolähetin-vastaanottimille. Mobiilipäätelaitteissa myös koko ja virrankulutus ovat tärkeässä asemassa, asettaen näin omat vaatimuksensa laitteistolle. Tällaisissa rakenteissa analogia-digitaalimuunninten suorituskykyä on pitkään pidetty pullonkaulana nykyaikaisten digitaalisten signaalinkäsittelytekniikoiden tarjoaman potentiaalin hyödyntämiselle. Tämän seurauksena kvadratuuri ΣΔ-modulaattoriin perustuva analogia-digitaalimuunnos on esitetty lupaavana ratkaisuna. Reaaliseen rakenteeseen perustuvaa vastinetta tehokkaampi kohinanmuokkaus ja parempi sopivuus moderneihin kvadratuurivastaanottimiin, joissa hyödynnetään kompleksista signaalinkäsittelyä jo valmiiksi, tekevät muuntimesta erityisen mielenkiintoisen vaihtoehdon. Tässä diplomityössä esitellään kvadratuuri-ΣΔ-muunnoksen perusperiaatteet ja siihen liittyvät signaalimallit. Tämän lisäksi on myös tärkeää, perustoiminnallisuuden ymmärtämisen lisäksi, tiedostaa todelliseen piiritoteutukseen liittyvät väistämättömät epäideaalisuudet. I/Q prosessointia hyödyntävissä radiolaitteissa yksi tärkeimmistä tämän tyyppisistä ilmiöistä on kahden haaran välinen epäsovitus. Tästä johtuen sovitusongelma kvadratuuri ΣΔ muuntimissa analysoidaan tarkasti ja tietokonesimulaatioilla varmennetut tulokset esitetään tämän diplomityön loppupuolella. Työssä osoitetaan, että yllä mainittu epäsovitus on todellinen huolenaihe, erityisesti voimakkaan häiritsevän signaalin ollessa läsnä peilitaajuudella. Tällainen tilanne saattaa toteutua erityisesti laajakaistaisessa vastaanottimessa, jossa analogista selektiivisyyttä on pyritty vähentämään. Toisaalta analyysi osoittaa, että älykkäästi suunniteltu signaalisiirtofunktio auttaa tehokkaasti poistamaan modulaattorin takaisinkytkentähaarassa sijaitsevan epäsovituksen aiheuttamaa häiriötä. Tällä tavoin syntynyttä vääristymää pystytään vähentämään ilman ylimääräistä elektroniikkaa, jolloin kustannustehokkuudesta, tai muista vaatimuksista ei tarvitse tinkiä. Tämän lisäksi osoitetaan, että signaali- ja kohinakomponenttien toisistaan riippumaton peilaantuminen taajuuden suhteen luo haasteita perinteisille korjausalgoritmeille. Näin ollen kvadratuuri-ΣΔ-modulaattoreiden peilitaajuushäiriön hallitsemiseksi digitaalisen signaalinkäsittelyn keinoin tarvitaan uudenlaisia innovaatioita. Tällä tavoin voitaisiin myös välttää analogisen lisäelektroniikan aiheuttama kustannustehokkuus-, virrankulutus- ja kokovaatimusten vaarantuminen

Calibrated Continuous-Time Sigma-Delta Modulators

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry

A bandpass sigma delta modulator IF receiver

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaves 170-173).by Emilija Simic.M.Eng

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Quadrature sigma-delta modulators for reconfigurable A/D interface and dynamic spectrum access: analysis, design principles and digital post-processing

In the course of development of wireless communications and its modern applications, such as cloud technologies and increased consumption and sharing of multimedia, the radio spectrum has become increasingly congested. However, temporarily and spatially underused spectrum exists at the same time. For increasing the efficiency of spectrum usage, the concept of dynamic spectrum access (DSA) has been proposed. Ultimately, the DSA principle should be exploited also in cognitive radio (CR) receivers. Herein, this paradigm is approached from the receiver architecture point-of-view, considering software-defined radio (SDR) as a platform for the future DSA and CR devices. Particularly, an analog-to-digital converter (ADC) architecture exploiting quadrature ΣΔ modulator (QΣΔM) is studied in detail and proposed as a solution for the A/D interface, being identified as a performance bottleneck in SDRs. By exploiting a complex valued noise transfer function (NTF) enabled by the QΣΔM, the quantization precision of the ADC can be efficiently and flexibly focused on the frequency channels and the signals to be received and detected. At the same time, with a traditional non-noise-shaping ADC, the precision is distributed equally for the whole digitized frequency band containing also noninteresting signals. With a single QΣΔM, it is also possible to design a multiband NTF, allowing reception of multiple noncontiguous frequency channels without parallel receiver chains. Furthermore, with the help of digital control, the QΣΔM response can be reconfigured during operation. These capabilities fit in especially well with the above mentioned DSA and CR schemes, where the temporarily and spatially available channels might be scattered in frequency. From the implementation point-of-view, the effects of inherent implementation inaccuracies in the QΣΔM design need to be thoroughly understood. In this thesis, novel closed-form matrix-algebraic expressions are presented for analyzing the transfer functions of a general multistage QΣΔM with arbitrary number of arbitrary-order stages. Altogether, the signal response of an I/Q mismatched QΣΔM has four components. These are the NTF, an image noise transfer function, a signal transfer function (STF) and an image signal transfer function. The image transfer functions are provoked by the I/Q mismatches and define the frequency profile of the generated mirror-frequency interference (MFI), potentially deteriorating the quality of the received signal. This contribution of the thesis increases the understanding of different QΣΔM structures and allows the designers to study the effects of the implementation inaccuracies in closed form. In order to mitigate the MFI and improve the signal reception, a mirror-frequency rejecting STF design is proposed herein. This design is found to be effective against I/Q mismatches taking place in the feedback branches of the QΣΔM. This is shown with help of the closed-form analysis and confirmed with computer simulations on realistic reception scenarios. When a mismatch location independent MFI suppression is the desired option, it is a logical choice to do this processing in a digital domain, after the whole analog receiver front-end. However, this sets demands for the information to be digitized, i.e., the source of the MFI should be available also in the digital domain. For this purpose, a novel multiband transfer function design is proposed herein. In addition, a QΣΔM specific digital MFI compensation algorithm is developed. The compensation performance is illustrated in practical single- and multiband reception scenarios, considering desired signal bandwidths up to 20 MHz. In the multiband scenario, allowing reception and detection of noncontiguous frequency channels with a single receiver chain, the digital compensation processing is done sub-bandwise, securing reliable functionality also under strongly frequency-selective interference. In the applied single- and multistage QΣΔM architectures, the I/Q mismatches are considered in all the QΣΔM branches as well as in the preceding receiver front-end, modeling the challenging and realistic scenario where the whole receiver chain includes cascaded in-phase/quadrature (I/Q) mismatch sources. As a whole, developing digital MFI compensation is a significant step towards practical receiver implementations with QΣΔM ADCs. In consequence, this allows the exploitation of the multiband and reconfigurability properties. The proposed design can be implemented without additional analog components and is straightforwardly reconfigurable in dynamic signal conditions typical for DSA and CR systems, e.g., in case of frequency hand-off because of a primary user appearance. In addition, the digital post-compensation of the MFI eases the strict demands for the matching of the analog circuits in SDRs

Bandpass delta-sigma modulators for radio receivers

This thesis concerns discrete-time (DT) bandpass (BP) ΔΣ modulators targeted for intermediate frequency (IF) analog-to-digital (A/D) conversion in radio receivers. The receiver architecture adopted has to be capable of operating with different radio frequencies, channel bandwidths, and modulation techniques. This is necessary in order to achieve an extensive operating area and the possibility of utilizing a local mobile phone standard or a standard suitable for a specific service. The digital IF receiver is a good choice for a multi-mode and multi-band mobile phone receiver, because the signal demodulation and channel filtering are performed in the digital domain. This increases the flexibility of the receiver and relieves the design of the baseband part, but an A/D conversion with high dynamic range and low power dissipation is required. BP ΔΣ modulators are capable of converting a high-frequency narrow band signal and are therefore suitable for signal digitization in an IF receiver. First, the theory of BP ΔΣ modulators is introduced. It has been determined that resonators are the most critical circuit blocks in the implementation of a high performance BP ΔΣ modulator. Different DT resonator topologies are studied and a double-delay (DD) resonator is found to be the best candidate for a high quality resonator. A new DD switched-capacitor (SC) resonator structure has been designed. Furthermore, two evolution versions of the designed SC resonator are presented and their nonidealities are analyzed. The three designed DD SC resonator structures are a main point of the thesis, together with the experimental results. Five different DT BP ΔΣ modulator circuit structures have been implemented and measured. All three of the designed SC resonators are used in the implemented circuits. The experimental work consists of both single-bit and multi-bit structures, as well as both single-loop and cascade architectures. The circuits have been implemented with a 0.35 μm (Bi)CMOS technology and operate with a 3.0 V supply. The measured maximum signal-to-noise-and-distortion ratios (SNDRs) are 78 dB over 270 kHz (GSM), 75 dB over 1.25 MHz (IS-95), 69 dB over 1.762 MHz (DECT), and 48 dB over 3.84 MHz (WCDMA) bandwidths using a 60 MHz IF signal.reviewe