Beam-steering digital num array paramétrico

Engenharia Electrónica e TelecomunicaçõesActualmente existem diversos m etodos que permitem a realiza c~ao de beamsteering num altifalante param etrico. No entanto, a maioria dos m etodos e incapaz de proporcionar uma elevada resolu c~ao angular usando um projecto de hardware e ciente. Mais ainda, poucos s~ao os sistemas que proporcionam um controlo do beam de pot^encia em tempo real. Neste documento, e proposta uma nova abordagem para colmatar estes problemas tirando partido da alta frequ^encia inerente a modula c~ao sigmadelta. Esta implementa c~ao leva a um projecto compacto que proporciona uma elevada resolu cao angular associada a uma solu c~ao de baixo custo e com baixo consumo de pot^encia devido ao uso de apenas uma DAC sigmadelta. O sistema implementado sobre FPGA alia a natural alta frequ^encia dum modulador sigma-delta ao uso dum unico shift-register para introduzir os atrasos necess arios a realiza c~ao de beam-steering. A escolha do atraso adequado e feita com o uso de multiplexers que encaminham os diversos sinais sigma-delta para as sa das do sistema desejadas.Several methods enable a steerable beam using an parametric loudspeaker. However, many of them are not able to use a high angular resolution with an e cient design. More, even the ability to change the beam steering in real time is neglected by several methods. In this document, we propose a new approach to the beam-steering problem using the intrinsic high frequency of a sigma-delta digital to analog converter conjugated with online con gurable digital delays obtained only through a programmable wide shift-register. This implementation leads to a real time beam-steering with a simple digital processing block that enables a high resolution angle. Additionally the use of a sigma-delta DAC provides a low-cost, highly integrated and energy e cient system using only a DAC. The implemented system takes advantage of the high frequency of the digital signal from the sigma-delta modulator allied with the use of a shiftregister to obtain the ne time delays necessary to do the beam-steering. The several outputs delays are chosen between the sigma-delta signals in the shift-register using a group of multiplexers

Implementation of the onboard ADC and DAC on the Spartan 3E FPGA platform.

The objective of this project is to first interface the on board ADC and DAC available in the Spartan 3E FPGA platform, so that the real signals too can be processed by the FPGA board. Thus first of all, the ADC was interfaced and the results were observed via ChipScope Pro. Then the DAC was interfaced and checked if it was working or not. Finally both were operated together, where registers were used to store the values of the digital data obtained from the ADC and then sent to the DAC for the reconstruction of the original signal, which could be observed via a DSO. ADC is a prime requirement whenever real-world signals come into play, hence interfacing the ADC is of great use and help in using the real-world signals for our use and further processing to extract vital information. DAC also aids in the said process similarly. The basic aim being that a given input signal should output exactly or nearly exactly the given input signal after having it passed through the ADC and the DAC

Beam-steerng digital num array paramétrico

Mestrado em Engenharia Electrónica e TelecomunicaçõesActualmente existem diversos m etodos que permitem a realiza c~ao de beamsteering num altifalante param etrico. No entanto, a maioria dos m etodos e incapaz de proporcionar uma elevada resolu c~ao angular usando um projecto de hardware e ciente. Mais ainda, poucos s~ao os sistemas que proporcionam um controlo do beam de pot^encia em tempo real. Neste documento, e proposta uma nova abordagem para colmatar estes problemas tirando partido da alta frequ^encia inerente a modula c~ao sigmadelta. Esta implementa c~ao leva a um projecto compacto que proporciona uma elevada resolu cao angular associada a uma solu c~ao de baixo custo e com baixo consumo de pot^encia devido ao uso de apenas uma DAC sigmadelta. O sistema implementado sobre FPGA alia a natural alta frequ^encia dum modulador sigma-delta ao uso dum unico shift-register para introduzir os atrasos necess arios a realiza c~ao de beam-steering. A escolha do atraso adequado e feita com o uso de multiplexers que encaminham os diversos sinais sigma-delta para as sa das do sistema desejadas.Several methods enable a steerable beam using an parametric loudspeaker. However, many of them are not able to use a high angular resolution with an e cient design. More, even the ability to change the beam steering in real time is neglected by several methods. In this document, we propose a new approach to the beam-steering problem using the intrinsic high frequency of a sigma-delta digital to analog converter conjugated with online con gurable digital delays obtained only through a programmable wide shift-register. This implementation leads to a real time beam-steering with a simple digital processing block that enables a high resolution angle. Additionally the use of a sigma-delta DAC provides a low-cost, highly integrated and energy e cient system using only a DAC. The implemented system takes advantage of the high frequency of the digital signal from the sigma-delta modulator allied with the use of a shiftregister to obtain the ne time delays necessary to do the beam-steering. The several outputs delays are chosen between the sigma-delta signals in the shift-register using a group of multiplexers

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V

Embedded demonstrator for audio manipulation

Demonstration of embedded systems is a good way to motivate and recruit students to a future career in electronics. For Department of Electronics and Telecommunication at the Norwegian University of Science and Technology (NTNU), it is thus desirable to have an embedded demonstrator that gives the pupils an insight in what is actually possible when studying electronics at the university, a system that the department may present at different occasions. A good embedded demonstrator provides an interesting presentation of one or more topics related to electronics, and should be presented together with relevant theory in order to provide a level of education to the user.This report covers the implementation of an embedded demonstrator for audio manipulation on Altera's DE2 development and education board. The system is specified to demonstrate signal processing subjects like sampling and filtering through manipulation of analog audio signals. The main modules in the system are the Cyclone II 2C35 FPGA from Altera, running a Nios II soft-CPU, and a Wolfson WM8731 audio-codec. The specification of their operation is made with background in pedagogics theory in order to make the most interesting demonstration. To realize this specification, the system incorporates several design features for both activation and motivation of the user.The audio manipulator provides possibilities for comparison between different sample rates and filter characteristics in real-time operation. This makes the system well suited for practical demonstration of signal processing theory. Due to the presentation of perceivable results, in addition to the implementation of a user interface for interaction, the implemented audio demonstrator is considered to be a well suited platform for demonstration of topics related to electronics

New Hardware Architecture for Low-Cost Functional Test Systems Applications to HDMI generation

English: Development of a new test hardware architecture for functional test systems. Development of a proof-of-concept prototype for HDMI generation.Castellano: Desarrollo de una nueva arquitectura para equipos de test destinados a máquinas de test funcional de PCBs. Desarrollo de un prototipo de demostración destinado a la generación de HDMI.Català: Desenvolupament d'una nova arquitectura per equips de test destinats a màquines de test funcional de PCB. Desenvolupament d'un prototip de demostració destinat a generació d'HDM

Jitter reduction techniques for digital audio.

by Tsang Yick Man, Steven.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 94-99).ABSTRACT --- p.iACKNOWLEDGMENT --- p.iiLIST OF GLOSSARY --- p.iiiChapter 1 --- INTRODUCTION --- p.1Chapter 1.1 --- What is the jitter ？ --- p.3Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ？ --- p.4Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4Chapter 2.1.1 --- Digital data problem --- p.7Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9Chapter 2.3 --- Waveform distortion --- p.12Chapter 2.4 --- Logic induced jitter --- p.17Chapter 2.4.1 --- Digital noise mechanisms --- p.20Chapter 2.4.2 --- Different types of D-type flop-flip chips are linked below for ease of comparison --- p.21Chapter 2.4.3 --- Ground bounce --- p.22Chapter 2.5 --- Power supply high frequency noise --- p.23Chapter 2.6 --- Interface Jitter --- p.25Chapter 2.7 --- Cross-talk --- p.28Chapter 2.8 --- Inter-Symbol-Interference (ISI) --- p.28Chapter 2.9 --- Baseline wander --- p.29Chapter 2.10 --- Noise jitter --- p.30Chapter 2.11 --- FIFO jitter reduction chips --- p.31Chapter 3 --- JITTER REDUCTION TECHNIQUES --- p.33Chapter 3.1 --- Why using two-stage phase-locked loop (PLL ) ？Chapter 3.1.1 --- The PLL circuit components --- p.35Chapter 3.1.2 --- The PLL timing specifications --- p.36Chapter 3.2 --- Analog phase-locked loop (APLL ) circuit usedin second stage --- p.38Chapter 3.3 --- All digital phase-locked loop (ADPLL ) circuit used in second stage --- p.40Chapter 3.4 --- ADPLL design --- p.42Chapter 3.4.1 --- "Different of K counter value of ADPLL are listed for comparison with M=512, N=256, Kd=2" --- p.46Chapter 3.4.2 --- Computer simulated results and experimental results of the ADPLL --- p.47Chapter 3.4.3 --- PLL design notes --- p.58Chapter 3.5 --- Different of the all digital Phase-Locked Loop (ADPLL ) and the analogue Phase-Locked Loop (APLL ) are listed for comparison --- p.65Chapter 3.6 --- Discrete transistor oscillator --- p.68Chapter 3.7 --- Discrete transistor oscillator circuit operation --- p.69Chapter 3.8 --- The advantage and disadvantage of using external discrete oscillator --- p.71Chapter 3.9 --- Background of using high-precision oscillators --- p.72Chapter 3.9.1 --- The temperature compensated crystal circuit operation --- p.73Chapter 3.9.2 --- The temperature compensated circuit design notes --- p.75Chapter 3.10 --- The discrete voltage reference circuit operation --- p.76Chapter 3.10.1 --- Comparing the different types of Op-amps that can be used as a voltage comparator --- p.79Chapter 3.10.2 --- Precaution of separate CMOS chips Vdd and Vcc --- p.80Chapter 3.11 --- Board level jitter reduction method --- p.81Chapter 3.12 --- Digital audio interface chips --- p.82Chapter 3.12.1 --- Different brand of the digital interface receiver (DIR) chips and clock modular are listed for comparison --- p.84Chapter 4. --- APPLICATION CIRCUIT BLOCK DIAGRAMS OF JITTER REDUCTION AND CLOCK RECOVERY --- p.85Chapter 5 --- CONCLUSIONS --- p.90Chapter 5.1 --- Summary of the research --- p.90Chapter 5.2 --- Suggestions for further development --- p.92Chapter 5.3 --- Instrument listing that used in this thesis --- p.93Chapter 6 --- REFERENCES --- p.94Chapter 7 --- APPENDICES --- p.100Chapter 7.1.1 --- Phase instability in frequency dividersChapter 7.1.2 --- The effect of clock tree on Tskew on ASIC chipChapter 7.1.3 --- Digital audio transmission----Why jitter is important?Chapter 7.1.4 --- Overview of digital audio interface data structuresChapter 7.1.5 --- Typical frequency Vs temperature variations curve of Quartz crystalsChapter 7.2 --- IC specification used in these research projec

Low Latency Audio Processing

PhDLatency in the live audio processing chain has become a concern for audio engineers and system designers because significant delays can be perceived and may affect synchronisation of signals, limit interactivity, degrade sound quality and cause acoustic feedback. In recent years, latency problems have become more severe since audio processing has become digitised, high-resolution ADCs and DACs are used, complex processing is performed, and data communication networks are used for audio signal transmission in conjunction with other traffic types. In many live audio applications, latency thresholds are bounded by human perceptions. The applications such as music ensembles and live monitoring require low delay and predictable latency. Current digital audio systems either have difficulties to achieve or have to trade-off latency with other important audio processing functionalities. This thesis investigated the fundamental causes of the latency in a modern digital audio processing system: group delay, buffering delay, and physical propagation delay and their associated system components. By studying the time-critical path of a general audio system, we focus on three main functional blocks that have the significant impact on overall latency; the high-resolution digital filters in sigma-delta based ADC/DAC, the operating system to process low latency audio streams, and the audio networking to transmit audio with flexibility and convergence. In this work, we formed new theory and methods to reduce latency and accurately predict latency for group delay. We proposed new scheduling algorithms for the operating system that is suitable for low latency audio processing. We designed a new system architecture and new protocols to produce deterministic networking components that can contribute the overall timing assurance and predictability of live audio processing. The results are validated by simulations and experimental tests. Also, this bottom-up approach is aligned with the methodology that could solve the timing problem of general cyber-physical systems that require the integration of communication, software and human interactions

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements