An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

A real-time FPGA-based implementation of a high-performance MIMO-OFDM mobile WiMAX transmitter

The Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) is considered a key technology in modern wireless-access communication systems. The IEEE 802.16e standard, also denoted as mobile WiMAX, utilizes the MIMO-OFDM technology and it was one of the first initiatives towards the roadmap of fourth generation systems. This paper presents the PHY-layer design, implementation and validation of a high-performance real-time 2x2 MIMO mobile WiMAX transmitter that accounts for low-level deployment issues and signal impairments. The focus is mainly laid on the impact of the selected high bandwidth, which scales the implementation complexity of the baseband signal processing algorithms. The latter also requires an advanced pipelined memory architecture to timely address the datapath operations that involve high memory utilization. We present in this paper a first evaluation of the extracted results that demonstrate the performance of the system using a 2x2 MIMO channel emulation.Postprint (published version

Wilis: Architectural Modeling of Wireless Systems

The performance of a wireless system depends on the wireless channel as well as the algorithms used in the transceiver pipelines. Because physical phenomena affect transceiver pipelines in difficult to predict ways, detailed simulation of the entire transceiver system is needed to evaluate even a single processing block. Further, some protocol validations require simulation of rare events (say, 1 bit error in 109 bits), which means the protocol must simulate for a long enough time for such events to materialize. This requirement coupled with the heavy computation typical of most physical-layer processing, rules out pure software solutions. In this paper we describe WiLIS, an FPGA-based hybrid hardware-software system designed to facilitate the development of wireless protocols. We then use WiLIS to evaluate several microarchitectures for measuring very low bit-error rates (BER). We demonstrate, for the first time, that the recently proposed SoftPHY can be implemented efficiently in hardware

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

Software Defined Channel Sounder for Power Line Communications

Most power line channel sounders are based on expensive lab instruments. This work presents an alternative based on software defined radio platforms. These can be later also employed as communication modems, decreasing costs and deployment times. We implemented and evaluated two channel sounding techniques: frequency hopping and sliding correlator. The results suggest that frequency hopping might be a better candidate for power line channels due to the expected low signal-to-noise ratio

MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems

Peer ReviewedPostprint (published version

Wideband active envelope load-pull for robust power amplifier and transistor characterisation

The advent of fourth generation (4G) wireless communication with available modulation bandwidth ranging from 1 MHz to 20 MHz is starting to emerge. The linear modulation technique being employed means that the power amplifiers that support the standards need to have high degree of linearity. By nature, however, all power amplifiers are non-linear. Load-pull measurement system provides anindispensable non-linear tool for the characterization of power amplifier and transistor for linearity enhancement. Conventional passive or active load-pull has delay problem that get worse as the modulation frequency is increased beyond few MHz. Furthermore in order to provide robust non-linear measurement, load-pull system needs to provide bandwidth at least five times the modulation bandwidth by including the fifth-order inter-modulation (IMD5). This thesis presents, for the first time, delay compensation on the unique active envelope load-pull architecture providing constant impedance for bandwidth up to 20 MHz. In doing so, it provides a superior load-pull measurement and also the ability to directly control in-band impedances. Artificial variations imposed on the in-band impedances offer further insight on power amplifier and transistor behaviours under wideband multi-tone stimulus.EThOS - Electronic Theses Online ServiceGBUnited Kingdo