First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

Design of low order high OSR discrete time delta-sigma modulator for audio applications

Tato diplomová práce si klade za cíl seznámit čtenáře se základním konceptem a principy jednosmyčkových modulátorů . Diplomová práce ozřejmuje čtenáři problematiku delta-sigma () modulátorů s jednou zpětnovazební smyčkou. Zabývá se základními principy převzorkování u číslicově-analogových převodníků a rozšiřuje je o teorii tvarování spektra šumu. Vycházeje z této teorie jsou navrženy tři jednosmyčkové modulátory, které běží na 1024 OSR jako alternativa k běžně používáným modulátorům vysokých řádů. Modulátory jsou implementovány do FPGA společně s rekonstrukčním filtrem a podpůrnými bloky. Nakonec byl zkonstruován hardwarový prototyp pro vyhodnocení implementace navrženého DAC.This master thesis aims to familiarize the reader with the basic concept and fundamental principles of single-loop modulators. It offers an alternative to a high-order modulators in the form of low-order modulators running at high oversampling rate. Low order modulators have better modulator loop stability, which can be leveraged to get higher noise-shaping power at lower frequencies. A complete digital to analog converter is proposed, mostly implemented in an FPGA. A hardware prototype was built to evaluate the DAC implementation.

Implementation of the onboard ADC and DAC on the Spartan 3E FPGA platform.

The objective of this project is to first interface the on board ADC and DAC available in the Spartan 3E FPGA platform, so that the real signals too can be processed by the FPGA board. Thus first of all, the ADC was interfaced and the results were observed via ChipScope Pro. Then the DAC was interfaced and checked if it was working or not. Finally both were operated together, where registers were used to store the values of the digital data obtained from the ADC and then sent to the DAC for the reconstruction of the original signal, which could be observed via a DSO. ADC is a prime requirement whenever real-world signals come into play, hence interfacing the ADC is of great use and help in using the real-world signals for our use and further processing to extract vital information. DAC also aids in the said process similarly. The basic aim being that a given input signal should output exactly or nearly exactly the given input signal after having it passed through the ADC and the DAC

Beam-steering digital num array paramétrico

Engenharia Electrónica e TelecomunicaçõesActualmente existem diversos m etodos que permitem a realiza c~ao de beamsteering num altifalante param etrico. No entanto, a maioria dos m etodos e incapaz de proporcionar uma elevada resolu c~ao angular usando um projecto de hardware e ciente. Mais ainda, poucos s~ao os sistemas que proporcionam um controlo do beam de pot^encia em tempo real. Neste documento, e proposta uma nova abordagem para colmatar estes problemas tirando partido da alta frequ^encia inerente a modula c~ao sigmadelta. Esta implementa c~ao leva a um projecto compacto que proporciona uma elevada resolu cao angular associada a uma solu c~ao de baixo custo e com baixo consumo de pot^encia devido ao uso de apenas uma DAC sigmadelta. O sistema implementado sobre FPGA alia a natural alta frequ^encia dum modulador sigma-delta ao uso dum unico shift-register para introduzir os atrasos necess arios a realiza c~ao de beam-steering. A escolha do atraso adequado e feita com o uso de multiplexers que encaminham os diversos sinais sigma-delta para as sa das do sistema desejadas.Several methods enable a steerable beam using an parametric loudspeaker. However, many of them are not able to use a high angular resolution with an e cient design. More, even the ability to change the beam steering in real time is neglected by several methods. In this document, we propose a new approach to the beam-steering problem using the intrinsic high frequency of a sigma-delta digital to analog converter conjugated with online con gurable digital delays obtained only through a programmable wide shift-register. This implementation leads to a real time beam-steering with a simple digital processing block that enables a high resolution angle. Additionally the use of a sigma-delta DAC provides a low-cost, highly integrated and energy e cient system using only a DAC. The implemented system takes advantage of the high frequency of the digital signal from the sigma-delta modulator allied with the use of a shiftregister to obtain the ne time delays necessary to do the beam-steering. The several outputs delays are chosen between the sigma-delta signals in the shift-register using a group of multiplexers

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

In this paper, the limitations of digital-to-analog (D/A) conversion by Digital Pulse Width Modulation (DPWM) are addressed and the novel Dyadic Digital Pulse Modulation (DDPM) technique for all-digital, low cost, high resolution, Nyquist-rate D/A conversion is proposed. Thanks to the spectral characteristics of the new modulation, in particular, the requirements of the filter needed to extract the baseband component of DPWM signals can be significantly released so that to be suitable to inexpensive integration on silicon in analog interfaces for nanoscale integrated systems. After the new DDPM technique and its properties are introduced on a theoretical basis, the implementation of a D/A converter (DAC) based on the proposed modulation is addressed and its performance in terms of noise and linearity is discussed. A 16-bit DDPM-DAC prototype is finally synthesized on a field-programmable gate array (FPGA) and experimentally characterized