Study of heterogeneous and reconfigurable architectures in the communication domain

One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role.</p><p style=&quot;line-height: 20px;&quot;> On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of <i>ATE</i> complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems

FPGA-Based Realisation of SDR with OFDM Tranceiver

Software-defined radio architecture is the key point of next generation communication systems in which some of the functional units are designed as software on a reconfigurable processor. This paper proposes the physical layer architecture of SDR with modified orthogonal frequency division multiplexing (OFDM). One of the main drawbacks of OFDM is that its high peak-to-average reduction (PAPR) ratio. The PAPR can be reduced using filtering and adaptive peak windowing method with Kaiser window. The adaptive window method finds the positions of maximum peak values using a peak detector in the signal and applies the window function with variable parameter. The radix 2 scalable N point FFT algorithm is used in the system. The mapping of the information signal is done with BPSK, PSK, and 16 QAM modulation. According to the signal-to- noise ratio (SNR) value, the type of modulation can be selected. Decoding of the OFDM signal in the receiver is done with Viterbi decoding algorithm. The communication system simulation is done in MATLAB and the baseband operations are implemented on Xilinx FPGA.Defence Science Journal, Vol. 65, No. 3, May 2015, pp.233-239, DOI: http://dx.doi.org/10.14429/dsj.65.601

Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA

The Viterbi algorithm is commonly applied in a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this thesis, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance

A hardware spinal decoder

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel alpha-beta incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters. We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.Irwin Mark Jacobs and Joan Klein Jacobs Presidential FellowshipIntel Corporation (Fellowship)Claude E. Shannon Research Assistantshi

A common operator for FFT and FEC decoding

International audienceIn the Software Radio context, the parametrization is becoming an important topic especially when it comes to multistandard designs. This paper capitalizes on the Common Operator technique to present new common structures for the FFT and FEC decoding algorithms. A key benefit of exhibiting common operators is the regular architecture it brings when implemented in a Common Operator Bank (COB). This regularity makes the architecture open to future function mapping and adapted to accommodated silicon technology variability through dependable design

Implementation of WiMAX physical layer baseband processing blocks in FPGA

This project thesis elaborates on designing a baseband processing blocks for Worldwide Interoperability for Microwave Access (WiMAX) physical layer using an FPGA. WiMAX provides broadband wireless access and uses OFDM as the essential modulation technique. The channel performance is badly affected due to synchronization mismatches between the transmitter and receiver ends so the transmitted signal received is not reliable as the OFDM deals with high data rate. This thesis includes the theory and concepts behind OFDM, WiMAX IEEE 802.16d standard and other blocks algorithms, its architectures used for designing as well as a presentation of how they are implemented. Here Altera’s FPGA has been used for targeting to the EP4SGX70HF35C2 device of the Stratix IV family. WiMAX use sophisticated digital signal processing techniques, which typically require a large number of mathematical computations. Here Stratix IV devices are ideally suited for these kinds of complex tasks because the DSP blocks have a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. The WiMAX physical layer baseband processing architecture consists of various major modules which were simulated block wise in order to check its giving the correct output as required. The coding style used here is VHDL. The sub-blocks have been synthesized using Altera Quartus II v11. 0 and simulated using ModelSim Altera Edition 6.6d