INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Single-Photon Avalanche Diodes in CMOS Technologies for Optical Communications

As optical communications may soon supplement Wi-Fi technologies, a concept known as visible light communications (VLC), low-cost receivers must provide extreme sensitivity to alleviate attenuation factors and overall power usage within communications link budgets. We present circuits with an advantage over conventional optical receivers, in that gain can be applied within the photodiode thus reducing the need for amplification circuits. To achieve this, single-photon avalanche diodes (SPADs) can be implemented in complementary metal-oxide-semiconductor (CMOS) technologies and have already been investigated in several topologies for VLC. The digital nature of SPADs removes the design effort used for low-noise, high-gain but high-bandwidth analogue circuits. We therefore present one of these circuit topologies, along with some common design and performance metrics. SPAD receivers are however not yet mature prompting research to take low-level parameters up to the communications level

High speed event-based visual processing in the presence of noise

Standard machine vision approaches are challenged in applications where large amounts of noisy temporal data must be processed in real-time. This work aims to develop neuromorphic event-based processing systems for such challenging, high-noise environments. The novel event-based application-focused algorithms developed are primarily designed for implementation in digital neuromorphic hardware with a focus on noise robustness, ease of implementation, operationally useful ancillary signals and processing speed in embedded systems

Parallel reconfigurable single photon avalanche diode array for optical communications

There is a pressing need to develop alternative communications links due to a number of physical phenomena, limiting the bandwidth and energy efficiency of wire-based systems or economic factors such as cost, material-supply reliability and environmental costs. Networks have moved to optical connections to reduce costs, energy use and to supply high data rates. A primary concern is that current optical-detection devices require high optical power to achieve fast data rates with high signal quality. The energy required therefore, quickly becomes a problem. In this thesis, advances in single-photon avalanche diodes (SPADs) are utilised to reduce the amount of light needed and to reduce the overall energy budget. Current high performance receivers often use exotic materials, many of which have severe environmental impact and have cost, supply and political restrictions. These present a problem when it comes to integration; hence silicon technology is used, allowing small, mass-producible, low power receivers. A reconfigurable SPAD-based integrating receiver in standard 130nm imaging CMOS is presented for links with a readout bandwidth of 100MHz. A maximum count rate of 58G photon/s is observed, with a dynamic range of ≈ 79dB, a sensitivity of ≈ −31.7dBm at 100MHz and a BER of ≈ 1x10−9. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32x32 SPAD array, achieves a minimum dead time of 5.9ns, and a median dark count rate (DCR) of 2.5kHz per SPAD. High noise devices can be weighted or removed to optimise the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed. The thesis concludes that data can be captured well with such a device but more electrical energy is needed at the receiver due to its fundamental operation. Overall, optical power can be reduced, allowing significant savings in either transmitter power or the transmission length, along with the advantages of an integrated digital chip

New Architectures and Circuits for Pushing the Dynamic Range and Multiplexing Boundaries of CMOS-Integrated Sensors

Over the last decades, CMOS-integrated sensors have made impressive progress in performance, form-factor, and energy-efficiency for various applications such as imaging, physical/chemical sensing, bio/health monitoring. In the era of the artificial intelligence (AI) and the internet-of-things (IoT), such CMOS-integrated sensors are essential for massive and comprehensive data acquisition, where sensing range (or dynamic range), signal fidelity (or signal-to-noise ratio), and data throughput are key factors. Towards pushing the boundaries of such sensing capabilities, in this dissertation, novel sensing architectures are presented with energy/area-efficient circuit design techniques for multi-channel CMOS optical sensors and neural interfaces. The first topic is a fully-integrated, wide linear dynamic range optical sensor array combining linear and single-photon avalanche diode operation within each pixel. A pulse-counting readout scheme provides in-pixel digitization in an area-efficient manner for both operation modes, enabling fully parallel measurement across the array. The proposed dual-mode optical sensor array alternately requires high-voltage(10-20 V) and low-voltage supply (2-5 V) for reverse bias of the photodiodes, which is provided by a reconfigurable, closed-loop high-voltage charge pump in the same substrate. An 8 x 8 array architecture along with the dual-mode bias generator is fabricated in a general purpose 180 nm CMOS process and demonstrates 129 dB dynamic range while maintaining linear photoresponse operating with a dual-mode frame rate of 20 Hz. The second topic is a new approach for applying code-division multiplexing (CDM) to current-mode and voltage-mode sensor arrays with analog-domain orthogonal encoding directly in a shared, single analog-front-end circuit, which enables simultaneous readout for multiple sensors. The approach is applied to a 8 x 16 array of CMOS-integrated photodetectors and implemented in a general purpose 180 nm CMOS process, where the 16 channel CDM-based oversampling readout achieves an SNR improvement of more than 12 dB compared with time-division multiplexing at the same sampling rate. In addition, a CDM-based neural recording architecture is presented, which offers a significant tolerance to interference that can be injected through long cables

Optimized PET module for both pixelated and monolithic scintillator crystals

[eng] Time-of-Flight Positron Emission Tomography (TOF-PET) scanners demand fast and efficient photo-sensors and scintillators coupled to fast readout electronics. Nowadays, there are two main configurations regarding the scintillator crystal geometry: the segmented or pixelated and the monolithic approach. Depending on the cost, spatial resolution and time requirements of the PET module, one can choose between one or another. The pixelated crystal is the most extensive configuration on TOF-PET scanners as the coincidence time resolution is better compared to the monolithic. On the contrary, monolithic scintillator crystals for Time-of-Flight Positron Emission Tomography (ToF-PET) are increasing in popularity this last years due to their performance potential and price in front of the commonly used segmented crystals. On one hand, monolithic blocks allows to determine 3D information of the gamma-ray interaction inside the crystal, which enables the possibility to correct the parallax error (radial astigmatism) at off-center positions within a PET scanner, resulting in an improvement of the spatial resolution of the device. On the other hand, due to the simplicity during the crystal manufacturing process as well as for the detector design, the price is reduced compared to a regular pixelated detector. The thesis starts with the use of HRFlexToT, an ASIC developed in this group, as the readout electronics for measurements with single pixelated crystals coupled to different SiPMs. These measurements show an energy linearity error of 3% and an energy resolution below 10% of the 511 keV photopeak. Single Photon Time Resolution (SPTR) measurements performed using an FBK SiPM NUV-HD (4 mm x 4 mm pixel size) and a Hamamatsu SiPM S13360-3050CS gave a 141 ps and 167 ps FWHM respectively. Coincidence Time Resolution (CTR) measurements with small cross-section pixelated crystals (LFS crystal, 3 m x 3 mm x 20 mm ) coupled to a single Hamamatsu SiPM S13360-3050CS provides a CTR of 180 ps FWHM. Shorter crystals (LSO:Ce Ca 0.4%) coupled to a Hamamatsu S13360-3050CS SiPM or FBK-NUVHD yields a CTR of 117 ps and 119 ps respectively. Then, the results with different monolithic crystals and SiPM sensors using HRFlexToT ASIC will be presented. A Lutetium Fine Silicate (LFS) of 25 mm x 25 mm x 20 mm, a small LSO:Ce Ca 0.2% of 8 mm x 8 mm x 5 mm and a Lutetium-Yttrium Oxyorthosilicate (LYSO) of 25 mm x 25 mm x 10 mm has been experimentally tested. After subtracting the TDC contribution (82 ps FWHM), a coincidence time resolution of 244 ps FWHM for the small LFS crystal and 333 ps FWHM for the largest LFS one is reported. Additionally, a novel time calibration correction method for CTR improvement that involves a pico-second pulsed laser will be detailed. In the last part of the dissertation, a new developed simulation framework that will enable the cross-optimization of the whole PET system will be explained. It takes into consideration the photon physics interaction in the scintillator crystal, the sensor response (sensor size, pixel pitch, dead area, capacitance) and the readout electronics behavior (input impedance, noise, bandwidth, summation). This framework has allowed us to study a new promising approach that will help reducing the CTR parameter by segmenting a large area SiPM into "m" smaller SiPMs and then summing them to recover all the signal spread along these smaller sensors. A 15% improvement on time resolution is expected by segmenting a 4 mm x 4 mm single sensor into 9 sensors of 1.3 mm x 1.3 mm with respect to the case where no segmentation is applied.[cat] Aquesta tesi tenia com a objectiu la fabricació i avaluació d'un prototip per a detecció de fotons gamma en aplicació per imatge mèdica, més concretament en Tomografia per Emissió de Positrons amb mesura de temps de vol (TOF-PET). L'avaluació del mòdul va començar fent una caracterització completa del chip (ASIC) anomenat HRFlexToT, una versió nova i millorada de l'antic chip FlexToT, desenvolupat i fabricat pel grup de la Unitat Tecnològica del ICC de la Universitat de Barcelona. Aquesta avaluació inicial del chip compren des de la comprovació de les funcionalitats bàsiques fins a la generació d'un test automàtic per generar les gràfiques de linealitat corresponents durant el test elèctric. Un cop donat per bo, es va muntar en una placa demostrada, també ideada per l'equip d'enginyers del grup, i ja quedava llesta per realitzar les mesures pertinents. Tot seguit, es varen realitzar les mesures òptiques, que incloïa mesures de Singe Photon Time Resolution (SPTR) i de Coincidence Time Resolution (CTR). Aquest valors actuen com a figures de mèrit a l'hora de comparar les prestacions amb d'altres ASICs competidors del HRFlexToT. Es van obtenir valors de 60 ps de resposta pel que respecta al SPTR i de 115 ps de CTR en cristalls segmentats, una millora entorn del 20-30% respecte a la versió predecessora del chip. Aquests valors mostren ser el límit de l'estat de l'art actual i amb aquesta idea es van començar a fer altres mesures, en aquest cas amb cristall monolítics, blocs grans llegits per diversos fotosensors de les empreses Hamamatsu i FBK. Per altra banda, es va provar el funcionament del ASIC en configuració anomenada monolítica, on el cristall centellejador s'utilitza en blocs grans en coptes d’emprar cristalls segmentats, això abarateix el cost total del detector. Aquesta configuració degrada les propietats de CTR, un paràmetre crític a l'hora de tenir un producte bo i eficient. S’han obtingut mesures de 250 ps de CTR amb aquesta configuració, d’on es pot dir que l’HRFlexToT es trobar a l’estat de l’art de la tecnologia electrònica dedicada a TOF-PET amb cristalls segmentats i monolítics. Finalment, es va desenvolupar una nova eina simulació que consisteix en un sistema híbrid entre un simulador físic i un electrònic per tal de tenir una idea del comportament complet del mòdul detector. Una solució que ningú havia provat fins ara o que no es pot trobar en la literatura

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range