Resource efficient on-node spike sorting

Current implantable brain-machine interfaces are recording multi-neuron activity by utilising multi-channel, multi-electrode micro-electrodes. With the rapid increase in recording capability has come more stringent constraints on implantable system power consumption and size. This is even more so with the increasing demand for wireless systems to increase the number of channels being monitored whilst overcoming the communication bottleneck (in transmitting raw data) via transcutaneous bio-telemetries. For systems observing unit activity, real-time spike sorting within an implantable device offers a unique solution to this problem. However, achieving such data compression prior to transmission via an on-node spike sorting system has several challenges. The inherent complexity of the spike sorting problem arising from various factors (such as signal variability, local field potentials, background and multi-unit activity) have required computationally intensive algorithms (e.g. PCA, wavelet transform, superparamagnetic clustering). Hence spike sorting systems have traditionally been implemented off-line, usually run on work-stations. Owing to their complexity and not-so-well scalability, these algorithms cannot be simply transformed into a resource efficient hardware. On the contrary, although there have been several attempts in implantable hardware, an implementation to match comparable accuracy to off-line within the required power and area requirements for future BMIs have yet to be proposed. Within this context, this research aims to fill in the gaps in the design towards a resource efficient implantable real-time spike sorter which achieves performance comparable to off-line methods. The research covered in this thesis target: 1) Identifying and quantifying the trade-offs on subsequent signal processing performance and hardware resource utilisation of the parameters associated with analogue-front-end. Following the development of a behavioural model of the analogue-front-end and an optimisation tool, the sensitivity of the spike sorting accuracy to different front-end parameters are quantified. 2) Identifying and quantifying the trade-offs associated with a two-stage hybrid solution to realising real-time on-node spike sorting. Initial part of the work focuses from the perspective of template matching only, while the second part of the work considers these parameters from the point of whole system including detection, sorting, and off-line training (template building). A set of minimum requirements are established which ensure robust, accurate and resource efficient operation. 3) Developing new feature extraction and spike sorting algorithms towards highly scalable systems. Based on waveform dynamics of the observed action potentials, a derivative based feature extraction and a spike sorting algorithm are proposed. These are compared with most commonly used methods of spike sorting under varying noise levels using realistic datasets to confirm their merits. The latter is implemented and demonstrated in real-time through an MCU based platform.Open Acces

Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation

In this paper, we present a new method for neural spike sorting based on Continuous Time (CT) signal processing. A set of CT based features are proposed and extracted from CT sampled pulses, and a complete event-driven spike sorting algorithm that performs classification based on these features is developed. Compared to conventional methods for spike sorting, the hardware implementation of the proposed method does not require any synchronisation clock for logic circuits, and thus its power consumption depend solely on the spike activity. This has been implemented using a variable quantisation step CT analogue to digital converter (ADC) with custom digital logic that is driven by level crossing events. Simulation results using synthetic neural data shows a comparable accuracy compared to template matching (TM) and Principle Components Analysis (PCA) based discrete sampled classification

A scalable 32 channel neural recording and real-time FPGA based spike sorting system

This demo presents a scalable a 32-channel neural recording platform with real-time, on-node spike sorting ca- pability. The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo ® nano FPGA; and an FX3 USB 3.0 controller. Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated

A 32-Channel MCU-Based Feature Extraction and Classification for Scalable on-Node Spike Sorting

This paper describes a new hardware-efficient method and implementation for neural spike sorting based on selection of a channel-specific near-optimal subset of fea- tures given a larger predefined set. For each channel, real- time classification is achieved using a simple decision matrix that considers the features that provide the highest separability determined through off-line training. A 32-channel system for on- line feature extraction and classification has been implemented in an ARM Cortex-M0+ processor. Measured results of the hardware platform consumes 268 W per channel during spike sorting (includes detection). The proposed method provides at least x10 reduction in computational requirements compared to literature, while achieving an average classification error of less than 10% across wide range of datasets and noise levels

A caloritronics-based Mott neuristor

Machine learning imitates the basic features of biological neural networks to efficiently perform tasks such as pattern recognition. This has been mostly achieved at a software level, and a strong effort is currently being made to mimic neurons and synapses with hardware components, an approach known as neuromorphic computing. CMOS-based circuits have been used for this purpose, but they are non-scalable, limiting the device density and motivating the search for neuromorphic materials. While recent advances in resistive switching have provided a path to emulate synapses at the 10 nm scale, a scalable neuron analogue is yet to be found. Here, we show how heat transfer can be utilized to mimic neuron functionalities in Mott nanodevices. We use the Joule heating created by current spikes to trigger the insulator-to-metal transition in a biased VO2 nanogap. We show that thermal dynamics allow the implementation of the basic neuron functionalities: activity, leaky integrate-and-fire, volatility and rate coding. By using local temperature as the internal variable, we avoid the need of external capacitors, which reduces neuristor size by several orders of magnitude. This approach could enable neuromorphic hardware to take full advantage of the rapid advances in memristive synapses, allowing for much denser and complex neural networks. More generally, we show that heat dissipation is not always an undesirable effect: it can perform computing tasks if properly engineered

Real-time neural signal processing and low-power hardware co-design for wireless implantable brain machine interfaces

Intracortical Brain-Machine Interfaces (iBMIs) have advanced significantly over the past two decades, demonstrating their utility in various aspects, including neuroprosthetic control and communication. To increase the information transfer rate and improve the devices’ robustness and longevity, iBMI technology aims to increase channel counts to access more neural data while reducing invasiveness through miniaturisation and avoiding percutaneous connectors (wired implants). However, as the number of channels increases, the raw data bandwidth required for wireless transmission also increases becoming prohibitive, requiring efficient on-implant processing to reduce the amount of data through data compression or feature extraction. The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time wireless BMI applications. The specific original contributions include the following: Firstly, a new method has been developed for hardware-efficient spike detection, which achieves state-of-the-art spike detection performance and significantly reduces the hardware complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike detection threshold, we have improved the adaptiveness of spike detection. This eventually allows the spike detection to overcome the signal degradation that arises due to scar tissue growth around the recording site, thereby ensuring enduringly stable spike detection results. The long-term decoding performance, as a consequence, has also been improved notably. Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing transmission bandwidth by at least 30% with minor decoding performance degradation. In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike detection algorithms and applying them to reduce the data bandwidth and improve neural decoding performance. The software-hardware co-design approach is essential for the next generation of wireless brain-machine interfaces with increased channel counts and a highly constrained hardware budget. The fundamental aim of this research is to develop methods for high-performance neural spike processing co-designed within low-power hardware that is scaleable for real-time wireless BMI applications. The specific original contributions include the following: Firstly, a new method has been developed for hardware-efficient spike detection, which achieves state-of-the-art spike detection performance and significantly reduces the hardware complexity. Secondly, a novel thresholding mechanism for spike detection has been introduced. By incorporating firing rate information as a key determinant in establishing the spike detection threshold, we have improved the adaptiveness of spike detection. This eventually allows the spike detection to overcome the signal degradation that arises due to scar tissue growth around the recording site, thereby ensuring enduringly stable spike detection results. The long-term decoding performance, as a consequence, has also been improved notably. Thirdly, the relationship between spike detection performance and neural decoding accuracy has been investigated to be nonlinear, offering new opportunities for further reducing transmission bandwidth by at least 30\% with only minor decoding performance degradation. In summary, this thesis presents a journey toward designing ultra-hardware-efficient spike detection algorithms and applying them to reduce the data bandwidth and improve neural decoding performance. The software-hardware co-design approach is essential for the next generation of wireless brain-machine interfaces with increased channel counts and a highly constrained hardware budget.Open Acces

SenseBack - An implantable system for bidirectional neural interfacing

Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. In this article, to resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary ex-vivo and in-vivo preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with ±20 V of compliance and up to 315 μA of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To the best of our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals