pandapower - an Open Source Python Tool for Convenient Modeling, Analysis and Optimization of Electric Power Systems

pandapower is a Python based, BSD-licensed power system analysis tool aimed at automation of static and quasi-static analysis and optimization of balanced power systems. It provides power flow, optimal power flow, state estimation, topological graph searches and short circuit calculations according to IEC 60909. pandapower includes a Newton-Raphson power flow solver formerly based on PYPOWER, which has been accelerated with just-in-time compilation. Additional enhancements to the solver include the capability to model constant current loads, grids with multiple reference nodes and a connectivity check. The pandapower network model is based on electric elements, such as lines, two and three-winding transformers or ideal switches. All elements can be defined with nameplate parameters and are internally processed with equivalent circuit models, which have been validated against industry standard software tools. The tabular data structure used to define networks is based on the Python library pandas, which allows comfortable handling of input and output parameters. The implementation in Python makes pandapower easy to use and allows comfortable extension with third-party libraries. pandapower has been successfully applied in several grid studies as well as for educational purposes. A comprehensive, publicly available case-study demonstrates a possible application of pandapower in an automated time series calculation

Proceedings of the NSSDC Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications

The proceedings of the National Space Science Data Center Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications held July 23 through 25, 1991 at the NASA/Goddard Space Flight Center are presented. The program includes a keynote address, invited technical papers, and selected technical presentations to provide a broad forum for the discussion of a number of important issues in the field of mass storage systems. Topics include magnetic disk and tape technologies, optical disk and tape, software storage and file management systems, and experiences with the use of a large, distributed storage system. The technical presentations describe integrated mass storage systems that are expected to be available commercially. Also included is a series of presentations from Federal Government organizations and research institutions covering their mass storage requirements for the 1990's

Forward converter current fed equalizer for lithium based batteries in ultralight electrical vehicles

In this paper, the concept of a forward balancing technique fed by a buck converter for lithium-based batteries in Electrical Vehicle (EV) applications is investigated. The proposed active topology equalizes eight cells in a series in a battery pack, by using a forward converter for each battery pack and the whole battery packs, using a buck converter. The battery bank consists of four battery packs, which are in series. Therefore, the proposed system will equalize 32 cells in series. In this paper, the proposed circuit employs a single transistor used in a Zero Voltage Switch (ZVS) for the forward converter. In practice, this means a capacitor in parallel with the switch at the same time a demagnetizing of the transformer is obtained. The circuit realizes a low Electromagnetic Interference (EMI) and reduces ringing. To overcome the problem of many pins on a coil former, the transformer secondary windings are made by using hairpin winding, on a ring core. It permits, e.g., having eight secondaries and uniform output voltages. Each secondary winding is made by two hairpin turns using two zero-Ohm resistors in series. The proposed topology has less components and circuitry, and it can equalize multiple battery packs by using a single buck converter and several forward converters for each battery pack. Experimental and simulation results are performed to verify the viability of the proposed topology

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast

Brain networks for temporal adaptation, anticipation, and sensory-motor integration in rhythmic human behavior

Human interaction often requires the precise yet flexible interpersonal coordination of rhythmic behavior, as in group music making. The present fMRI study investigates the functional brain networks that may facilitate such behavior by enabling temporal adaptation (error correction), prediction, and the monitoring and integration of information about ‘self’ and the external environment. Participants were required to synchronize finger taps with computer-controlled auditory sequences that were presented either at a globally steady tempo with local adaptations to the participants' tap timing (Virtual Partner task) or with gradual tempo accelerations and decelerations but without adaptation (Tempo Change task). Connectome-based predictive modelling was used to examine patterns of brain functional connectivity related to individual differences in behavioral performance and parameter estimates from the adaptation and anticipation model (ADAM) of sensorimotor synchronization for these two tasks under conditions of varying cognitive load. Results revealed distinct but overlapping brain networks associated with ADAM-derived estimates of temporal adaptation, anticipation, and the integration of self-controlled and externally controlled processes across task conditions. The partial overlap between ADAM networks suggests common hub regions that modulate functional connectivity within and between the brain's resting-state networks and additional sensory-motor regions and subcortical structures in a manner reflecting coordination skill. Such network reconfiguration might facilitate sensorimotor synchronization by enabling shifts in focus on internal and external information, and, in social contexts requiring interpersonal coordination, variations in the degree of simultaneous integration and segregation of these information sources in internal models that support self, other, and joint action planning and prediction

Sequence reproduction, single trial learning, and mimicry based on a mammalian-like distributed code for time

Animals learn tasks requiring a sequence of actions over time. Waiting a given time before taking an action is a simple example. Mimicry is a complex example, e.g. in humans, humming a brief tune you have just heard. Re-experiencing a sensory pattern mentally must involve reproducing a sequence of neural activities over time. In mammals, neurons in prefrontal cortex have time-dependent firing rates that vary smoothly and slowly in a stereotyped fashion. We show through modeling that a Many are Equal computation can use such slowly-varying activities to identify each timepoint in a sequence by the population pattern of activity at the timepoint. The MAE operation implemented here is facilitated by a common inhibitory conductivity due to a theta rhythm. Sequences of analog values of discrete events, exemplified by a brief tune having notes of different durations and intensities, can be learned in a single trial through STDP. An action sequence can be played back sped up, slowed down, or reversed by modulating the system that generates the slowly changing stereotyped activities. Synaptic adaptation and cellular post-hyperpolarization rebound contribute to robustness. An ability to mimic a sequence only seconds after observing it requires the STDP to be effective within seconds.Comment: 18 page

Flowtune: Flowlet Control for Datacenter Networks

Rapid convergence to a desired allocation of network resources to endpoint traffic has been a long-standing challenge for packet-switched networks. The reason for this is that congestion control decisions are distributed across the endpoints, which vary their offered load in response to changes in application demand and network feedback on a packet-by-packet basis. We propose a different approach for datacenter networks, flowlet control, in which congestion control decisions are made at the granularity of a flowlet, not a packet. With flowlet control, allocations have to change only when flowlets arrive or leave. We have implemented this idea in a system called Flowtune using a centralized allocator that receives flowlet start and end notifications from endpoints. The allocator computes optimal rates using a new, fast method for network utility maximization, and updates endpoint congestion-control parameters. Experiments show that Flowtune outperforms DCTCP, pFabric, sfqCoDel, and XCP on tail packet delays in various settings, converging to optimal rates within a few packets rather than over several RTTs. Our implementation of Flowtune handles 10.4x more throughput per core and scales to 8x more cores than Fastpass, for an 83-fold throughput gain

Solar electric propulsion system tests

Design and performance of solar-powered electric propulsion system for interplanetary space exploratio

Real-Time Simulation of a Smart Inverter

abstract: With the increasing penetration of Photovoltaic inverters, there is a necessity for recent PV inverters to have smart grid support features for increased power system reliability and security. The grid support features include voltage support, active and reactive power control. These support features mean that inverters should have bidirectional power and communication capabilities. The inverter should be able to communicate with the grid utility and other inverter modules. This thesis studies the real time simulation of smart inverters using PLECS Real Time Box. The real time simulation is performed as a Controller Hardware in the Loop (CHIL) real time simulation. In this thesis, the power stage of the smart inverter is emulated in the PLECS Real Time Box and the controller stage of the inverter is programmed in the Digital Signal Processor (DSP) connected to the real time box. The power stage emulated in the real time box and the controller implemented in the DSP form a closed loop smart inverter. This smart inverter, with power stage and controller together, is then connected to an OPAL-RT simulator which emulates the power distribution system of the Arizona State University Poly campus. The smart inverter then sends and receives commands to supply power and support the grid. The results of the smart inverter with the PLECS Real time box and the smart inverter connected to an emulated distribution system are discussed under various conditions based on the commands received by the smart inverter.Dissertation/ThesisMasters Thesis Electrical Engineering 201