A model of a generalized chip structure

Three distinct levels can be distinguished in the design of digital systems: architecture, implementation and realization. Description methods are available at each level assuming that at the realization level components such as nands and nors are used. The introduction of programmable components, such as microprocessors and programmable input/output chips, which now form the basis elements at the realization level, forces to reconsider these description methods

User microprogrammable processors for high data rate telemetry preprocessing

The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors

An automatic microprogramming system.

by Wu Kam-wah.Bibliography: leaves [129]-[130]Thesis (M.Ph.)--Chinese University of Hong Kong, 198

Estimators for Logic Minimization and Implementation Selection of Finite State machines

This paper considers two estimation problems which occur during the implementation design for a finite state machine (FSM). The first is a precise estimation of the reduction of a programmed logic array implementation (PLA) for a FSM by logic minimization. The second concerns selection of implementation alternatives based on such estimations. Estimations give the designer a quick overview of the impact of an optimization method for FSM implementation without running the actual time-consuming algorithms. The method uses curve-fitting on results found in literature for logic minimization preceded by state-assignment. Our estimations correlate by 0.97 to those results. State-graph statistics can also be used for selection of the most profitable optimization from a set of alternatives. We tested selection between a counter based implementation, partial state coding, state-assignment and topological partitioning. The goal is selection of the alternative which has the highest probability to deliver the largest minimization of the FSM. This selection method is also empirically verified by comparing its results with results obtained by running specific optimization algorithms on machines of the MCNC benchmark set

Stepwise decomposition in controlpath synthesis

A method is presented for the synthesis of the microarchitecture of controlpaths. This method is called stepwise decomposition. It focuses primarily on controlpaths of instruction set processors, however it is also applicable for more general Finite State Machine synthesis. Many of the current controlpath synthesis algorithms are based on a fixed microarchitecture, and an optimization of that microarchitecture. This stepwise decomposition method is able to synthesize microarchitectures in a range from a single PLA to multiple PLA/ROM configurations and optionally further down to hardwired, which makes it more flexible and better suited to a wider range of controlpaths than current synthesis methods. A sequence of decomposition steps, from coarse to detailed, is performed on the design to move it to the area of the design space where all constraints on space, floorplan and delay are satisfied. The method is currently implemented in APL

Microprogrammed Simulation System for General Purpose Register and Fixed Purpose Register Minicomputers

This thesis is a description of a microprogrammed simulation system for general purpose register and fixed purpose register minicomputers. Such systems aid in the efficiency in which assembler programs are developed for certain classes of minicomputers. The description is designed to instruct the reader in microprogramming techniques and how these techniques might be implemented.Computing and Information Science

An experiment in high-level microprogramming

This thesis describes an experiment in developing a true high-level microprogramming language for the Burroughs B1700 series of computers. Available languages for machine description both at a behavioural level and at a microprogramming level are compared and the conclusion drawn that none were suitable for our purpose and that it was necessary to develop a new language which we call SUILVEN. SUILVEN is a true high-level language with no machine-dependent features. It permits the exact specification of the size of abstract machine data areas (via the BITS declaration) and allows the user to associate structure with these data areas (via the TEMPLATE declaration), SUILVEN only permits the use of structured control statements (if-then-else, while-do etc.) - the go to statement is not a feature of the language. SUILVEN is compiled into microcode for the B1700 range of machines. The compiler is written in SNOBOL4 and uses a top-down recursive descent analysis technique, using abstract machines for PASCAL and the locally developed SASL, SUILVEN was compared with other high and low level languages. The conclusions drawn from this comparison were as follows: - (i) SUILVEN was perfectly adequate for describing simple S-machines (ii) SUILVEN lacked certain features for describing higher-level machines (iii) The needs of a machine description language and a microprogram implementation language are different and that it is unrealistic to attempt to combine these in a single language

Minicomputer Concepts

This thesis presents a study of concepts used in the design of minicomputers currently on the market. The material is drawn from research on sixteen minicomputer systems.Computing and Information Science

Recent technical advances in the computer industry and their future inmpact,

Includes bibliographical references.by Stuart E. Madnick