Technology and layout-related testing of static random-access memories

Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect—silicon SRAMs and GaAs SRAMs.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43015/1/10836_2004_Article_BF00972519.pd

Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation

As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide.Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens.The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy

A comprehensive review and performance evaluation in solar (PV) systems fault classification and fault detection techniques

The renewable energy industry is growing faster than ever before and in particular solar systems have significantly expanded. Abnormal conditions lead to a reduction in the maximum available power from solar (photovoltaic) systems. Thus, it is necessary to identification, detection, and monitoring of various faults in the PV system that they are the key factors to increase the efficiency, reliability, and lifetime of these systems. Up to now, faults on PV components and systems have been identified; some of them have physical damage on PV systems and some of them are electrical faults that occur on the DC side or AC side of the PV system. Here, the faults will be divided into groups based on their location of occurrence. This paper provides a comprehensive review of almost all PV system faults and fault detection techniques of PV system proposed in recent literature

Deep Learning for Enhanced Fault Diagnosis of Monoblock Centrifugal Pumps: Spectrogram-Based Analysis

Abstract The reliable operation of monoblock centrifugal pumps (MCP) is crucial in various industrial applications. Achieving optimal performance and minimizing costly downtime requires effectively detecting and diagnosing faults in critical pump components. This study proposes an innovative approach that leverages deep transfer learning techniques. An accelerometer was adopted to capture vibration signals emitted by the pump. These signals are then converted into spectrogram images which serve as the input for a sophisticated classification system based on deep learning. This enables the accurate identification and diagnosis of pump faults. To evaluate the effectiveness of the proposed methodology, 15 pre-trained networks including ResNet-50, InceptionV3, GoogLeNet, DenseNet-201, ShuffleNet, VGG-19, MobileNet-v2, InceptionResNetV2, VGG-16, NasNetmobile, EfficientNetb0, AlexNet, ResNet-18, Xception, ResNet101 and ResNet-18 were employed. The experimental results demonstrate the efficacy of the proposed approach with AlexNet exhibiting the highest level of accuracy among the pre-trained networks. Additionally, a meticulous evaluation of the execution time of the classification process was performed. AlexNet achieved 100.00% accuracy with an impressive execution (training) time of 17 s. This research provides invaluable insights into applying deep transfer learning for fault detection and diagnosis in MCP. Using pre-trained networks offers an efficient and precise solution for this task. The findings of this study have the potential to significantly enhance the reliability and maintenance practices of MCP in various industrial settings

No Fault Found events in maintenance engineering Part 2: Root causes, technical developments and future research

This is the second half of a two paper series covering aspects of the no fault found (NFF) phenomenon, which is highly challenging and is becoming even more important due to increasing complexity and criticality of technical systems. Part 1 introduced the fundamental concept of unknown failures from an organizational, behavioral and cultural stand point. It also reported an industrial outlook to the problem, recent procedural standards, whilst discussing the financial implications and safety concerns. In this issue, the authors examine the technical aspects, reviewing the common causes of NFF failures in electronic, software and mechanical systems. This is followed by a survey on technological techniques actively being used to reduce the consequence of such instances. After discussing improvements in testability, the article identifies gaps in literature and points out the core areas that should be focused in the future. Special attention is paid to the recent trends on knowledge sharing and troubleshooting tools; with potential research on technical diagnosis being enumerated

Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA

The Viterbi algorithm is commonly applied in a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this thesis, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance

Evaluating the impact of an enhanced energy performance standard on load-bearing masonry domestic construction: Understanding the gap between designed and real performance: lessons from Stamford Brook.

This report is aimed at those with interests in the procurement, design and construction of new dwellings both now and in the coming years as the Government’s increasingly stringent targets for low and zero carbon housing approach. It conveys the results of a research project, carried out between 2001 and 2008, that was designed to evaluate the extent to which low carbon housing standards can be achieved in the context of a large commercial housing development. The research was led by Leeds Metropolitan University in collaboration with University College London and was based on the Stamford Brook development in Altrincham, Cheshire. The project partners were the National Trust, Redrow and Taylor Wimpey and some 60 percent of the planned 700 dwelling development has been completed up to June 2008. As the UK house building industry and its suppliers grapple with the challenges of achieving zero carbon housing by 2016, the lessons arising from this project are timely and of considerable value. Stamford Brook has demonstrated that designing masonry dwellings to achieve an enhanced energy standard is feasible and that a number of innovative approaches, particularly in the area of airtightness, can be successful. The dwellings, as built, exceed the Building Regulations requirements in force at the time but tests on the completed dwellings and longer term monitoring of performance has shown that, overall, energy consumption and carbon emissions, under standard occupancy, are around 20 to 25 percent higher than design predictions. In the case of heat loss, the discrepancy can be much higher. The report contains much evidence of considerable potential but points out that realising the design potential requires a fundamental reappraisal of processes within the industry from design and construction to the relationship with its supply chain and the development of the workforce. The researchers conclude that, even when builders try hard, current mainstream technical and organisational practices together with industry cultures present barriers to consistent delivery of low and zero carbon performance. They suggest that the underlying reasons for this are deeply embedded at all levels of the house building industry. They point out also that without fundamental change in processes and cultures, technological innovations, whether they be based on traditional construction or modern methods are unlikely to reach their full potential. The report sets out a series of wide ranging implications for new housing in the UK, which are given in Chapter 14 and concludes by firmly declaring that cooperation between government, developers, supply chains, educators and researchers will be crucial to improvement. The recommendations in this report are already being put into practice by the researchers at Leeds Metropolitan University and University College London in their teaching and in further research projects. The implications of the work have been discussed across the industry at a series of workshops undertaken in 2008 as part of the LowCarb4Real project (see http://www.leedsmet.ac.uk/as/cebe/projects/lowcarb4real/index.htm). In addition, the learning is having an impact on the work of the developers (Redrow and Taylor Wimpey) who, with remarkable foresight and enthusiasm, hosted the project. This report seeks to make the findings more widely available and is offered for consideration by everyone who has a part to play in making low and zero carbon housing a reality

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits