Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

RECONFIGURABLE POWER AMPLIFIER WITH TUNABLE INTERSTAGE MATCHING NETWORK USING GaAs MMIC AND SURFACE-MOUNT TECHNOLOGY

As the demand of reconfigurable devices increases, the possibility of exploiting the interstage matching network in a two-stage amplifier to provide center frequency tuning capability is explored. While placement of tuning elements at the input and/or output matching network has some disadvantages, placement of tuning elements in the interstage absorbs the lossy components characteristics into useful attributes. The circuit design methodology includes graphical method to determine the bandpass topology that achieves high Q-contour on the Smith chart thus result in narrow bandwidth. T-section and π-section topologies are used to match reactive terminations provided by the first and second amplifier stages. The design methodology also includes utilization of interstage mismatch loss that decreases as increasing frequency to compensate for amplifier gain roll-off and equalize the gain at different tuning states. In prototype realization, three design configurations are discussed in this thesis: 1) a discrete design for operation between 0.1 – 0.9 GHz with the total layout area of 7.5 mm x 12.5 mm, 2) a partial monolithic design (Quasi-MMIC) for operation between 0.9 – 2.4 GHz that is 25 times smaller layout area compared to the discrete design, and 3) a conceptual design of integrated monolithic reconfigurable PA for operation between 0.9 – 2.4 GHz that is 130 times smaller layout area compared to the discrete design. One variant of the fabricated reconfigurable PA offers advantage of 4-states center frequency tuning from 1.37 GHz to 1.95 GHz with gain of 21.5 dB (+ 0.7 dB). The feasibility of interstage matching network as tuning elements in reconfigurable power amplifier has been explored. The input and output matching networks are fixed while the interstage impedances are varied using electronic switching (discrete SP4T and GaAs FET switches). The discrete design is suited for the operation at low frequency (fo < 1GHz), while monolithic implementation of the tunable interstage matching network is required for higher frequency operation due to size limitation and parasitic effects. The reconfigurable PA using MMIC tuner was designed at higher frequency to possibly cover GSM, CDMA, Bluetooth, and WiMAX frequency (0.9 – 2.4 GHz)

RECONFIGURABLE POWER AMPLIFIER WITH TUNABLE INTERSTAGE MATCHING NETWORK USING GaAs MMIC AND SURFACE-MOUNT TECHNOLOGY

As the demand of reconfigurable devices increases, the possibility of exploiting the interstage matching network in a two-stage amplifier to provide center frequency tuning capability is explored. While placement of tuning elements at the input and/or output matching network has some disadvantages, placement of tuning elements in the interstage absorbs the lossy components characteristics into useful attributes. The circuit design methodology includes graphical method to determine the bandpass topology that achieves high Q-contour on the Smith chart thus result in narrow bandwidth. T-section and π-section topologies are used to match reactive terminations provided by the first and second amplifier stages. The design methodology also includes utilization of interstage mismatch loss that decreases as increasing frequency to compensate for amplifier gain roll-off and equalize the gain at different tuning states. In prototype realization, three design configurations are discussed in this thesis: 1) a discrete design for operation between 0.1 – 0.9 GHz with the total layout area of 7.5 mm x 12.5 mm, 2) a partial monolithic design (Quasi-MMIC) for operation between 0.9 – 2.4 GHz that is 25 times smaller layout area compared to the discrete design, and 3) a conceptual design of integrated monolithic reconfigurable PA for operation between 0.9 – 2.4 GHz that is 130 times smaller layout area compared to the discrete design. One variant of the fabricated reconfigurable PA offers advantage of 4-states center frequency tuning from 1.37 GHz to 1.95 GHz with gain of 21.5 dB (+ 0.7 dB). The feasibility of interstage matching network as tuning elements in reconfigurable power amplifier has been explored. The input and output matching networks are fixed while the interstage impedances are varied using electronic switching (discrete SP4T and GaAs FET switches). The discrete design is suited for the operation at low frequency (fo < 1GHz), while monolithic implementation of the tunable interstage matching network is required for higher frequency operation due to size limitation and parasitic effects. The reconfigurable PA using MMIC tuner was designed at higher frequency to possibly cover GSM, CDMA, Bluetooth, and WiMAX frequency (0.9 – 2.4 GHz)

Wireless Power Transfer

Wireless power transfer techniques have been gaining researchers' and industry attention due to the increasing number of battery-powered devices, such as mobile computers, mobile phones, smart devices, intelligent sensors, mainly as a way to replace the standard cable charging, but also for powering battery-less equipment. The storage capacity of batteries is an extremely important element of how a device can be used. If we talk about battery-powered electronic equipment, the autonomy is one factor that may be essential in choosing a device or another, making the solution of remote powering very attractive. A distinction has to be made between the two forms of wireless power transmission, as seen in terms of how the transmitted energy is used at the receiving point: - Transmission of information or data, when it is essential for an amount of energy to reach the receiver to restore the transmitted information; - Transmission of electric energy in the form of electromagnetic field, when the energy transfer efficiency is essential, the power being used to energize the receiving equipment. The second form of energy transfer is the subject of this book

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

ENABLING TECHNOLOGY FOR WIRELESS POWER TRANSMISSION SUPPLY TO REMOTE EQUIPMENT IN CRITICAL LOGISTIC SCENARIOS

In this work were reviewed various issues concerning the supply of electrical and electronic equipment in presence of not wired physical scenarios have been reviewed. Possible solutions have been examined, in particular, the WPT solution one. Different technologies have been analyzed, with particular attention to resonant inductive type, examining applications and study approaches, as well as the pros and cons. Different prototypes have been studied, time after time, simulated designed and manufactured; these prototypes made possible the use of several methods of characterization. Finally an application, based on the same technology, for sensing purposes, specifically ground monitoring, has been optimized

Passive and active components development for broadband applications

Recently, GaN HEMTs have been proven to have numerous physical properties, resulting in transistors with greatly increased power densities when compared to the other well-established FET technologies. This advancement spurred research and product development towards power-band applications that require both high power and high efficiency over the wide band. Even though the use of multiple narrow band PAs covering the whole band has invariably led to better performance in terms of efficiency and noise, there is an associated increase in cost and in the insertion loss of the switches used to toggle between the different operating bands. The goal, now, of the new technology is to replace the multiple narrow band PAs with one broadband PA that has a comparable efficiency performance. In our study here, we have investigated a variety of wide band power amplifiers, including class AB PAs and their implementation in distributed and feedback PAs.Additionally, our investigation has included switching-mode PAs as they are well-known for achieving a relatively high efficiency. Besides having a higher efficiency, they are also less susceptible to parameter variations and could impose a lower thermal stress on the transistors than the conventional-mode PAs. With GaN HEMTs, we have demonstrated: a higher than 37 dBm output power and a more than 30% drain efficiency over 0.02 to 3 GHz for the distributed power amplifier; a higher than 30 dBm output power with more than a 22% drain efficiency over 0.1 to 5 GHz for the feedback amplifier; and at least a 43 dBm output power with a higher than 63% drain efficiency over 0.05 to 0.55 GHz for the class D PA. In many communication applications, however, achieving both high efficiency and linearity in the PA design is required. Therefore, in our research, we have evaluated several linearization and efficiency enhancement techniques.We selected the LInear amplification with Nonlinear Components (LINC) approach. Highly efficient combiner and novel efficiency enhancement techniques like the power recycling combiner and adaptive bias LINC schemes have been successfully developed and verified to achieve a combined high efficiency with a relatively high linearity

Design of Intellectual Property-Based Hardware Blocks Integrable with Embedded RISC Processors

The main focus of this thesis is to research methods, architecture, and implementation of hardware acceleration for a Reduced Instruction Set Computer (RISC) platform. The target platform is a single-core general-purpose embedded processor (the COFFEE core) which was developed by our group at Tampere University of Technology. The COFFEE core alone cannot meet the requirements of the modern applications due to the lack of several components of which the Memory Management Unit (MMU) is one of the prominent ones. Since the MMU is one of the main requirements of today’s processors, COFFEE with no MMU was not able to run an operating system. In the design of the MMU, we employed two additional micro-Translation-Lookaside Buffers (TLBs) to speed up the translation process, as well as minimizing congestions of the data/instruction address translations with a unified TLB. The MMU is tightly-coupled with the COFFEE RISC core through the Peripheral Control Block (PCB) interface of the core. The hardware implementation, alongside some optimization techniques and post synthesis results are presented, as well.Another intention of this work is to prepare a reconfigurable platform to send and receive data packets of the next generation wireless communications. Hence, we will further discuss a recently emerged wireless modulation technique known as Non-Contiguous Orthogonal Frequency Division Multiplexing (NC-OFDM), a promising technique to alleviate spectrum scarcity problem. However, one of the primary concerns in such systems is the synchronization. To that end, we developed a reconfigurable hardware component to perform as a synchronizer. The developed module exploits Partial Reconfiguration (PR) feature in order to reconfigure itself. Eventually, we will come up with several architectural choices for systems with different limiting factors such as power consumption, operating frequency, and silicon area. The synchronizer can be loosely-coupled via one of the available co-processor slots of the target processor, the COFFEE RISC core.In addition, we are willing to improve the versatility of the COFFEE core even in industrial use cases. Hence, we developed a reconfigurable hardware component capable of operating in the Controller Area Network (CAN) protocol. In the first step of this implementation, we mainly concentrate on receiving, decoding, and extracting the data segment of a CAN-based packet. Moreover, this hardware block can reconfigure itself on-the-fly to operate on different data frames. More details regarding hardware implementation issues, as well as post synthesis results are also presented. The CAN module is loosely-coupled with the COFFEE RISC processor through one of the available co-processor block

Smart Wireless Sensor Networks

The recent development of communication and sensor technology results in the growth of a new attractive and challenging area - wireless sensor networks (WSNs). A wireless sensor network which consists of a large number of sensor nodes is deployed in environmental fields to serve various applications. Facilitated with the ability of wireless communication and intelligent computation, these nodes become smart sensors which do not only perceive ambient physical parameters but also be able to process information, cooperate with each other and self-organize into the network. These new features assist the sensor nodes as well as the network to operate more efficiently in terms of both data acquisition and energy consumption. Special purposes of the applications require design and operation of WSNs different from conventional networks such as the internet. The network design must take into account of the objectives of specific applications. The nature of deployed environment must be considered. The limited of sensor nodes� resources such as memory, computational ability, communication bandwidth and energy source are the challenges in network design. A smart wireless sensor network must be able to deal with these constraints as well as to guarantee the connectivity, coverage, reliability and security of network's operation for a maximized lifetime. This book discusses various aspects of designing such smart wireless sensor networks. Main topics includes: design methodologies, network protocols and algorithms, quality of service management, coverage optimization, time synchronization and security techniques for sensor networks