Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/

In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay/sup 2/ product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound).Peer ReviewedPostprint (published version

Using MCD-DVS for dynamic thermal management performance improvement

With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a globally-asynchronous locally-synchronous (GALS) design style is employed. GALS, also known as multiple-clock domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers.Peer ReviewedPostprint (published version

A study of data coding technology developments in the 1980-1985 time frame, volume 2

The source parameters of digitized analog data are discussed. Different data compression schemes are outlined and analysis of their implementation are presented. Finally, bandwidth compression techniques are given for video signals

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

Wireless magnetic sensor network for road traffic monitoring and vehicle classification

Efficiency of transportation of people and goods is playing a vital role in economic growth. A key component for enabling effective planning of transportation networks is the deployment and operation of autonomous monitoring and traffic analysis tools. For that reason, such systems have been developed to register and classify road traffic usage. In this paper, we propose a novel system for road traffic monitoring and classification based on highly energy efficient wireless magnetic sensor networks. We develop novel algorithms for vehicle speed and length estimation and vehicle classification that use multiple magnetic sensors. We also demonstrate that, using such a low-cost system with simplified installation and maintenance compared to current solutions, it is possible to achieve highly accurate estimation and a high rate of positive vehicle classification

A high reliability battery management system

Over a period of some 5 years Canadian Astronautics Limited (CAL) has developed a system to autonomously manage, and thus prolong the life of, secondary storage batteries. During the development, the system was aimed at the space vehicle application using nickel cadmium batteries, but is expected to be able to enhance the life and performance of any rechargeable electrochemical couple. The system handles the cells of a battery individually and thus avoids the problems of over, and under, drive that inevitably occur in a battery of cells managed by an averaging system. This individual handling also allow cells to be totally bypassed in the event of failure, thus avoiding the losses associated with low capacity, partial short circuit, and the catastrophe of open circuit. The system has an optional capability of managing redundant batteries simultaneously, adding the advantage of on line reconditioning of one battery, while the other maintains the energy storage capability of the overall system. As developed, the system contains a dedicated, redundant, microprocessor, but the capability exists to have this computing capability time shared, or remote, and operating through a data link. As adjuncts to the basic management system CAL has developed high efficiency, polyphase, power regulators for charge and discharge power conditioning

Conceptual design study for Infrared Limb Experiment (IRLE)

The phase A engineering design study for the Infrared Limb Experiment (IRLE) instrument, the infrared portion of the Mesosphere-Lower Thermosphere Explorer (MELTER) satellite payload is given. The IRLE instrument is a satellite instrument, based on the heritage of the Limb Infrared Monitor of the Stratosphere (LIMS) program, that will make global measurements of O3, CO2, NO, NO2, H2O, and OH from earth limb emissions. These measurements will be used to provide improved understanding of the photochemistry, radiation, dynamics, energetics, and transport phenomena in the lower thermosphere, mesosphere, and stratosphere. The IRLE instrument is the infrared portion of the MELTER satellite payload. MELTER is being proposed to NASA Goddard by a consortium consisting of the University of Michigan, University of Colorado and NASA Langley. It is proposed that the Space Dynamics Laboratory at Utah State University (SDL/USU) build the IRLE instrument for NASA Langley. MELTER is scheduled for launch in November 1994 into a sun-synchronous, 650-km circular orbit with an inclination angle of 97.8 deg and an ascending node at 3:00 p.m. local time

Control speculation for energy-efficient next-generation superscalar processors

Conventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose selective throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).Peer ReviewedPostprint (published version

DyPS: Dynamic Processor Switching for Energy-Aware Video Decoding on Multi-core SoCs

In addition to General Purpose Processors (GPP), Multicore SoCs equipping modern mobile devices contain specialized Digital Signal Processor designed with the aim to provide better performance and low energy consumption properties. However, the experimental measurements we have achieved revealed that system overhead, in case of DSP video decoding, causes drastic performances drop and energy efficiency as compared to the GPP decoding. This paper describes DyPS, a new approach for energy-aware processor switching (GPP or DSP) according to the video quality . We show the pertinence of our solution in the context of adaptive video decoding and describe an implementation on an embedded Linux operating system with the help of the GStreamer framework. A simple case study showed that DyPS achieves 30% energy saving while sustaining the decoding performanc