On the transconductance of polysilicon thin film transistors

In order to achieve both driver and display capability for a number of display devices, TFT has attracted attention, model calculations are therefore presented for the grain boundary barrier height, in a polysilicon TFT considering the charge neutrality between the intrinsic free carriers and the grain boundary trap states. The formation of the potential barrier at a grain boundary is considered due to the trapping of carriers at the localized grain boundary trap states. The trapped charges, influenced by the gate bias voltage and the trapping states density, in turn, have been taken to deplete free carriers near the grain boundary in a device such as polysilicon TFT. The present predictions reveal that the barrier height diversely depends on the gate source voltage (VGS) of a TFT along with other crystal parameter. Finally to obtain the transconductance, the contributions of transverse and longitudinal grain boundary resistances are incorporated in the I-V characteristics of a TFT. For all values of grain size, the transconductance of the device is seen to increase initially with the gate voltage (VGS) which finally appears to be saturated. The dependence of the transconductance on grain size and drain voltage has been thoroughly explored. Good agreement with experimental results is achieved. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2299

Furnace and rapid thermal crystallization of amorphous GexSi1-x and Si for thin film transistors

The crystallization behavior of polycrystalline silicon (Si) and germanium-silicon alloys (GexSi1−x) from SiH4 and GeH4, where x is in the range of 0-0.32, has been investigated for thin film transistor (TFT) applications. Furnace anneals as well as rapid thermal anneal (RTA) and combinations of these two techniques have been used to crystallize amorphously deposited thin (≤100 nm) films. The effects of time and temperature for the furnace anneals and time, temperature and pulse rate for the RTA have been investigated. Smooth Si and GexSi1−x layers with a surface roughness ≤0.6 nm have been obtained using an initial Si layer for the GexSi1−x material, since GexSi1−x shows a nucleation problem on oxide surfaces which influences the resulting surface roughness and grain size. For TFT applications the optimal film properties cannot be obtained with a single crystallization anneal. Conventional furnace crystallization results in smooth layers with Si furnace crystallized films exhibiting small grains with many intra-grain defects. An average grain size of approximately 300 nm for Ge0.25Si0.75 and slightly larger grains for Ge0.32Si0.68 with less defects is obtained at lower temperature. RTA results for Si and GexSi1−x in fine grained material with lower defect density

Activation energy of polycrystalline silicon thin film transistor

The activation energy of a poly-Si thin film transistor is observed to be influenced by the grain size, trap state density and the inversion layer thickness. The present study aims to investigate these parameters theoretically so as to explore optimum conditions for the working of a polycrystalline silicon thin film transistor. Our computations have revealed that the activation energy decreases with the increase of gate bias for all values of grain size, trap states density and the inversion layer thickness. These findings are compared with the experimental results. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2201

Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions

Development in the world of technical and vocational education and training (TVET) on an ongoing basis is a challenge to the profession of the TVET-teachers to maintain their performance. The ability of teachers to identify the competencies required by their profession is very critical to enable them to make improvements in teaching and learning. For a broader perspective the competency needs of the labour market have to be matched by those developed within the vocational learning processes. Consequently, this study has focused on developing and validating the new empirical based TVET-teacher competency profile and evaluating teacher’s competency. This study combines both quantitative and qualitative research methodology that was designed to answer all the research questions. The new empirical based competency profile development and TVET-teacher evaluation was based upon an instructional design model. In addition, a modified Delphi technique has also been adopted throughout the process. Initially, 98 elements of competencies were listed by expert panel and rated by TVET institutions as important. Then, analysis using manual and statistical procedure found that 112 elements of competencies have emerged from seventeen (17) clusters of competencies. Prior to that, using the preliminary TVET-teacher competency profile, the level of TVETteacher competencies was found to be Proficient and the finding of 112 elements of competencies with 17 clusters was finally used to develop the new empirical based competency profile for MARA TVET-teacher. Mean score analysis of teacher competencies found that there were gaps in teacher competencies between MARA institutions (IKM) and other TVET institutions, where MARA-teacher was significantly better than other TVET teacher. ANOVA and t-test analysis showed that there were significant differences between teacher competencies among all TVET institutions in Malaysia. On the other hand, the study showed that teacher’s age, grade and year of experience are not significant predictors for TVET-teacher competency. In the context of mastering the competency, the study also found that three competencies are classified as most difficult or challenging, twelve competencies are classified as should be improved, and eight competencies are classified as needed to be trained. Lastly, to make NDTS implementation a reality for MARA the new empirical based competency profile and the framework for career development and training pathway were established. This Framework would serve as a significant tool to develop the knowledge based human resources needed. This will ensure that TVET-teachers at MARA are trained to be knowledgeable, competent, and professional and become a pedagogical leader on an ongoing basis towards a world class TVET-education system

Elaboration, characterization and simulation of thin film transistors based on Zinc Oxide

The thesis explores the field of polycrystalline semiconductor oxides, particularly zinc oxide (ZnO), as a key component in thin-film transistors (TFTs) crucial for electronic applications like active-matrix liquid crystal displays (AMLCDs). Utilizing numerical simulations with SILVACO ATLAS, the study investigates four main areas. First, the temperature effect on pc-ZnO TFTs is examined, revealing a temperature-dependent drain current with activation energy varying linearly from 0.57 eV to 0.071 eV across different gate voltages. Second, the impact of illumination on PC-ZnO TFTs at a low temperature of 280 K is studied, manipulating electric mobility and deep defects. Third, the grain size and boundary effects on nano-crystalline zinc oxide TFTs are explored through experimental and numerical analysis, demonstrating the influence of deposition temperature on grain size and subsequent transfer characteristics. Lastly, TFTs made of ZnO thin films deposited on various substrates are investigated, detailing the deposition process, pressure control, and annealing conditions. The research provides valuable insights into optimizing the performance of ZnO-based TFTs for electronic applications. Keywords: Elaboration, Characterization, Design, TFT, SILVACO ATLAS, Defects

Investigation of intrinsic channel characteristics of hydrogenated amorphous silicon thin-film transistors by gated-four-probe structure

We use a new hydrogenated amorphous silicon (a-Si:Ha-Si:H) device structure, the gated-four-probe a-Si:Ha-Si:H thin-film transistor (TFT), to investigate the intrinsic channel characteristics of inverted-staggered a-Si:Ha-Si:H TFTs without the influence of source/drain series resistances. The experimental results have shown that, for the conventional a-Si:Ha-Si:H TFT structure, the field-effect mobility, threshold voltage, and field-effect channel conductance activation energy have a strong dependence on a-Si:Ha-Si:H thickness and TFT channel length. On the other hand, for the gated-four-probe a-Si:Ha-Si:H TFT structure, these values are a-Si:Ha-Si:H thickness and TFT channel length independent, clearly indicating that this new a-Si:Ha-Si:H TFT structure can be effectively used to measure the channel intrinsic properties of a-Si:Ha-Si:H TFTs. © 1998 American Institute of Physics.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/70688/2/APPLAB-72-22-2874-1.pd

P‐64: UV‐Light‐Modified Polyimide Films for Liquid‐Crystal Alignment

Infrared, UV‐visible and X‐ray photoelectron spectroscopy measurements indicate that bond‐breaking and oxidation occur during broadband UV‐illumination of the polyimide film in the air. Surface tension and polarity are increased based on the measurements of contact angles. No obvious morphology change has been observed through atomic force microscopy analysis. While the polarized UV‐light generates a relatively small pretilt angle on a nonrubbed surface, it reduces the pretilt angle to some degree on a rubbed surface, depending upon the UV‐light polarization direction relative to the rubbing direction.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/92039/1/1.1833863.pd

Organic‐polymer thin‐film transistors for active‐matrix flat‐panel displays?

Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/92004/1/1.1825684.pd