In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed

Memristive Devices for Quantum Metrology

As a consequence of the redefinition of the International System of Units (SI), where units are defined in terms of fundamental physical constants, memristive devices represent a promising platform for quantum metrology. Coupling ionics with electronics, memristive devices can exhibit conductance levels quantized in multiples of the fundamental quantum of conductance G(0) = 2e(2)/h. Since the fundamental quantum of conductance G(0) is related only to physical constants that assume fixed value in the revised SI, memristive devices can be exploited for the practical realization of a quantum-based resistance standard that, differently from quantum-Hall based devices conventionally adopted as resistance standards, can operate in different ambient conditions (air, vacuum, harsh environment), in a wide range of temperatures and without the need of an applied magnetic field In this work, the possibility of using memristive devices for quantum metrology is critically discussed, based on recent experimental and theoretical advances on quantum conductance phenomena reported in literature. Thanks to the high operational speed, high scalability down to the nanometer scale, and CMOS compatibility, memristive devices allow on-chip implementation of a resistance standard required for the realization of self-calibrating electrical systems and equipment with zero-chain traceability in accordance with the revised SI

Experimental and Modeling Study of Metal–Insulator Interfaces to Control the Electronic Transport in Single Nanowire Memristive Devices

Memristive devices relying on redox-based resistive switching mechanisms represent promising candidates for the development of novel computing paradigms beyond von Neumann architecture. Recent advancements in understanding physicochemical phenomena underlying resistive switching have shed new light on the importance of an appropriate selection of material properties required to optimize the performance of devices. However, despite great attention has been devoted to unveiling the role of doping concentration, impurity type, adsorbed moisture, and catalytic activity at the interfaces, specific studies concerning the effect of the counter electrode in regulating the electronic flow in memristive cells are scarce. In this work, the influence of the metal-insulator Schottky interfaces in electrochemical metallization memory (ECM) memristive cell model systems based on single-crystalline ZnO nanowires (NWs) is investigated following a combined experimental and modeling approach. By comparing and simulating the electrical characteristics of single NW devices with different contact configurations and by considering Ag and Pt electrodes as representative of electrochemically active and inert electrodes, respectively, we highlight the importance of an appropriate choice of electrode materials by taking into account the Schottky barrier height and interface chemistry at the metal-insulator interfaces. In particular, we show that a clever choice of metal-insulator interfaces allows to reshape the hysteretic conduction characteristics of the device and to increase the device performance by tuning its resistance window. These results obtained from single NW-based devices provide new insights into the selection criteria for materials and interfaces in connection with the design of advanced ECM cells

Effect of Surface Variations on Resistive Switching

In this chapter, we study factors that dominate the interfacial resistive switching (RS) in memristive devices. We have also given the basic understanding of different type of RS devices which are predominantly interfacial in nature. In case of resistive random access memory (RRAM), the effect of surface properties on the bulk cannot be neglected as thickness of the film is generally below 100 nm. Surface properties are effected by redox reactions, interfacial layer formation, and presence of tunneling barrier. Surface morphology affects the band structure in the vicinity of interface, which in turn effects the movements of charge carriers. The effect of grain boundaries (GBs) and grain surfaces (GSs) on RS have also been discussed. The concentration of vacancies (Ov)/traps/defects is comparatively higher at GBs which leads to leakage current flow through the GBs predominantly. Such huge presence of charge carriers causes current flow through grain boundaries

The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and nonvolatile RAM (NVRAM), they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for Integrated Circuits (ICs). This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell's equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings of Royal Society

Picosecond Multilevel Resistive Switching in Tantalum Oxide Thin Films

The increasing demand for high-density data storage leads to an increasing interest in novel memory concepts with high scalability and the opportunity of storing multiple bits in one cell. A promising candidate is the redox-based resistive switch repositing the information in form of different resistance states. For reliable programming, the underlying physical parameters need to be understood. We reveal that the programmable resistance states are linked to internal series resistances and the fundamental nonlinear switching kinetics. The switching kinetics of Ta$_{2}$O$_{5}$-based cells was investigated in a wide range over 15 orders of magnitude from 250 ps to 10$^{5}$ s. We found strong evidence for a switching speed of 10 ps which is consistent with analog electronic circuit simulations. On all time scales, multi-bit data storage capabilities were demonstrated. The elucidated link between fundamental material properties and multi-bit data storage paves the way for designing resistive switches for memory and neuromorphic applications.Comment: Compiled PDF should contain 24 pages, 5 figures and 50 reference

Multilevel Modeling and Architectural Solutions for Emerging Technology Circuits

In the last decades, the main driving force behind the astonishing development of CMOS technology, was the transistor scaling process. The reduction of transistor sizes has granted a continuous boost in circuits performance. But now that the scaling process is reaching its physical limits, researchers are forcusing on new emerging technologies. Research on these new technologies is usually carried on using a traditional approach. Some studies concentrate on new devices without analyzing circuits based on them. Other studies analyze circuit architectures without considering devices characteristics and limitations. However, given that the nature of emerging technologies can be very different from CMOS, new research methodologies should be adopted. A clear link between device and architectural analysis is necessary to understand the true potential of the technology under study. The objective of this PhD thesis is the analysis of emerging technologies using an innovative methodology. Using complex and realistic circuits as benchmark, high level models are built incorporating low level device characteristics. This methodology strongly links device and architectural levels. The methodology was applied to two emerging technologies: NanoMagnet Logic (NML) and Nanoscale Application Specific Integrated Circuits (NASIC). A brief introduction of fundamental information on the two technologies is given in Chapter 1. The application of the methodology on NML technology is divided in two parts (Chapter 2): i) architecture-level timing and performance analysis and circuits optimization; (ii) area and power estimations using VHDL modeling. Starting from an exhaustive analysis of the effects and the consequences derived by the presence of loops in a complex NML sequential architecture, solutions have been proposed to address the problem of signal synchronization, and optimization techniques have been explored for performance maximization. Area and power estimations have been performed on multiple NML architectures in order to obtain a complete evaluation on the implementation of NanoMagnet Logic in comparison with the CMOS technology. Chapter 4 is dedicated to NASIC technology with basic principles described in Chapter 3. Basic computational blocks are implemented using a multilevel modeling approach. A detailed analysis of circuits' area and power estimations is obtained. Techniques to optimize the area of circuits at the cost of reduced throughput were also investigated. The research activity presented in this thesis highlights the development of an innovative methodology based on high-level models that embed information obtained from physical level simulations. By exploiting this methodology to different emerging technologies, such as NML and NASIC, it allows to eciently analyze circuits and therefore to bring architectural improvements

The Atomic Layer Deposition Technique for the Fabrication of Memristive Devices: Impact of the Precursor on Pre-deposited Stack Materials

Atomic layer deposition (ALD) is a standard technique employed to grow thin-film oxides for a variety of applications. We describe the technique and demonstrate its use for obtaining memristive devices. The metal/insulator/metal stack is fabricated by means of ALD-grown HfO2, deposited on top of a highly doped Si substrate with an SiO2 film and a Ti electrode. Enhanced device capabilities (forming free, self-limiting current, non-crossing hysteretic current-voltage features) are presented and discussed. Careful analysis of the stack structure by means of X-ray reflectometry, atomic force microscopy, and secondary ion mass spectroscopy revealed a modification of the device stack from the intended sequence, HfO2/Ti/SiO2/Si. Analytical studies unravel an oxidation of the Ti layer which is addressed for the use of the ozone precursor in the HfO2 ALD process. A new deposition process and the model deduced from impedance measurements support our hypothesis: the role played by ozone on the previously deposited Ti layer is found to determine the overall features of the device. Besides, these ALD-tailored multifunctional devices exhibit rectification capability and long enough retention time to deserve their use as memory cells in a crossbar architecture and multibit approach, envisaging other potential applications