On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits

Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories.  The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high.  Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time

Design of Low Power TPG for BIST Using Reconfigurable Johnson Counter

Worked in Self-Test assumes an essential job in testing of VLSI circuits. Test designs created utilizing design generator is utilized to test the Circuit under Test. Regular technique for test design age includes in Reconfigurable Johnson Counter and LFSR which needs in relationship between's progressive test vectors. A Modern Low Power test design is created utilizing Reconfigurable Johnson Counter and Accumulator. A Low Power utilization gadget is basic for battery worked gadgets. The system for delivering the test vectors for BIST is coded utilizing VHDL and reproductions were performed with ModelSim 10.0b

Testing PUF-Based Secure Key Storage Circuits

Abstract-Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The scheme targets high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The scheme reuses existing FE sub-blocks (for pattern generation and compression) to minimize the area overhead. The scheme is integrated in FE design and simulated; the results show that a SAF fault coverage of 95.1% can be realized with no more than 50k clock cycles at the cost of a negligible area overhead of only 2.2%. Higher fault coverage is possible to realize at extra cost

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Implementation of a real-time industrial web scanning system hardware architecture

None provided

PROTECTING DATA WITH FAULT CORRECTION SCRIPTS

A brand new architecture for matching the information protected by having an error-fixing code (ECC) is presented within this brief to lessen latency and complexity. Lately, however, triggered the attraction of increasingly more attentions in the academic field In line with the proven fact that the code word of the ECC is generally symbolized inside a systematic form composed from the raw data and also the parity information produced by encoding, the suggested architecture parallelizes the comparison from the data which from the parity information. To help lessen the latency and complexity, additionally, a brand new butterfly-created weight accumulator (BWA) is suggested for that efficient computation from the Hamming distance. Grounded around the BWA, the suggested architecture examines if the incoming data matches the stored data if your certain quantity of erroneous bits are remedied. For any (40, 33) code, the suggested architecture cuts down on the latency and also the hardware complexity by 32% and 9%, correspondingly, in comparison most abundant in recent implementation. Within the SA-based architecture, the comparison of two code words is invoked following the incoming tag is encoded. Therefore, the critical path includes a number of the encoding and also the n-bit comparison