VISA: Versatile impulse structure approximation for time-domain linear macromodeling

We develop a rational function macromodeling algorithm named VISA (Versatile Impulse Structure Approximation) for macromodeling of system responses with (discrete) time-sampled data. The ideas of Walsh theorem and complementary signal are introduced to convert the macromodeling problem into a non-pole-based Steiglitz-McBride (SM) iteration (a class of first- and second-order interpolations) without initial guess and eigenvalue computation. We demonstrate the fast convergence and the versatile macromodeling requirement adoption through a P-norm approximation expansion, using examples from practical data.published_or_final_versionThe 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Taipei, Taiwan, 18-21 January 2010. In Asia and South Pacific Design Automation Conference Proceedings, 2010, p. 37-4

An Opportunistic Error Correction Layer for OFDM Systems

In this paper, we propose a novel cross layer scheme to lower power\ud consumption of ADCs in OFDM systems, which is based on resolution\ud adaptive ADCs and Fountain codes. The key part in the new proposed\ud system is that the dynamic range of ADCs can be reduced by\ud discarding the packets which are transmitted over 'bad' sub\ud carriers. Correspondingly, the power consumption in ADCs can be\ud reduced. Also, the new system does not process all the packets but\ud only processes surviving packets. This new error correction layer\ud does not require perfect channel knowledge, so it can be used in a\ud realistic system where the channel is estimated. With this new\ud approach, more than 70% of the energy consumption in the ADC can be\ud saved compared with the conventional IEEE 802.11a WLAN system under\ud the same channel conditions and throughput. The ADC in a receiver\ud can consume up to 50% of the total baseband energy. Moreover, to\ud reduce the overhead of Fountain codes, we apply message passing and\ud Gaussian elimination in the decoder. In this way, the overhead is\ud 3% for a small block size (i.e. 500 packets). Using both methods\ud results in an efficient system with low delay

An Empirical Study of Thermal Attacks on Edge Platforms

Cloud-edge systems are vulnerable to thermal attacks as the increased energy consumption may remain undetected, while occurring alongside normal, CPU-intensive applications. The purpose of our research is to study thermal effects on modern edge systems. We also analyze how performance is affected from the increased heat and identify preventative measures. We speculate that due to the technology being a recent innovation, research on cloud-edge devices and thermal attacks is scarce. Other research focuses on server systems rather than edge platforms. In our paper, we use a Raspberry Pi 4 and a CPU-intensive application to represent thermal attacks on cloud-edge systems. We performed several experiments with the Raspberry Pi 4 and used stress-ng, a benchmarking tool available on Linux distributions, to simulate the attacks. The resulting effects displayed drastic increases in the temperature and power consumption. The key impact of our research is to highlight the following risks and mitigation plans: the vulnerability of cloud-edge systems from thermal attacks, the capability for the attacks to go unnoticed, to further the understanding of edge devices as well as the prevention of these attacks

Scalable Multiple Patterning Layout Decomposition Implemented by a Distribution Evolutionary Algorithm

As the feature size of semiconductor technology shrinks to 10 nm and beyond, the multiple patterning lithography (MPL) attracts more attention from the industry. In this paper, we model the layout decomposition of MPL as a generalized graph coloring problem, which is addressed by a distribution evolutionary algorithm based on a population of probabilistic model (DEA-PPM). DEA-PPM can strike a balance between decomposition results and running time, being scalable for varied settings of mask number and lithography resolution. Due to its robustness of decomposition results, this could be an alternative technique for multiple patterning layout decomposition in next-generation technology nodes

A non-linear analytic stress model for the analysis on the stress interaction between TSVs

Thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (∼18 ppm/◦C) and silicon (∼2.8 ppm/◦C) when the structure is exposed to a thermal budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to induce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to result in large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the finite element method and Mohr’s circle analysis. The stress characteristics are also measured by the atomic force microscope-raman technique at a nanometer level resolution. This nonlinear stress model for the strong interactions between TSVs results in an electron mobility change ~2-6% smaller than that resulting from a model that only considers the linear stress superposition principle

Software de base, métricas y aplicaciones en arquitecturas multiprocesador orientadas a cómputo de altas prestaciones

Caracterizar las arquitecturas multiprocesador distribuidas enfocadas especialmente a cluster y cloud computing, con énfasis en las que utilizan procesadores de múltiples núcleos (multicores y GPUs), con el objetivo de modelizarlas, estudiar su escalabilidad, analizar y predecir performance de aplicaciones paralelas, estudiar el consumo energético y su impacto en la perfomance así como desarrollar esquemas para detección y tolerancia a fallas en las mismas.\nProfundizar el estudio de arquitecturas basadas en GPUs y su comparación con clusters de multicores, así como el empleo combinado de GPUs y multicores en computadoras de alta perfomance. En particular estudiar perfomance en Clusters “híbridos”.\nAnalizar y desarrollar software de base para clusters de multicores y GPUs, tratando de optimizar el rendimiento.\nInvestigar arquitecturas multicore asimétricas, sus aplicaciones y el software de base de las mismas apuntando a optimizar el rendimiento de aplicaciones de propósito general.\nA partir del año 2013 se han incorporado nuevas líneas de interés:\n- Cloud computing, incluyendo aplicaciones de HPC sobre cloud.\n- El desarrollo de aplicaciones que integran Big Data y procesamiento sobre Cloud.\n- La utilización de los registros de hardware de los procesadores para la toma de diferentes decisiones en tiempo de ejecución.\n- El desarrollo de herramientas para la transformación de código heredado, buscando su optimización sobre arquitecturas paralelas.\nEs de hacer notar que este proyecto se coordina con otros proyectos en curso en el III-LIDI, relacionados con Algoritmos Paralelos, Sistemas Distribuidos y Sistemas de Tiempo Real.Eje: Procesamiento Distribuído y Paralel