High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Undersampling bandpass modulator architectures

Continuous-time delta sigma modulators -- Undersampling Delta-sigma modulators for radio receivers -- A novel continuous-time delta sigma modulator -- New delta modulator based on undersampling

Multi-standard digital FM receiver using limited IF architecture

Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 148-149).by Grant Y. Smith.S.B.and M.Eng

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Navigation/traffic control satellite mission study. Volume 3 - System concepts

Satellite network for air traffic control, solar flare warning, and collision avoidanc

Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages

University of Minnesota Ph.D. dissertation. June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xiv, 187 pages.Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is advantageous to digital circuits in terms of increased speed and lower power, analog circuits strongly suffer from this trend. This is becoming a crucial bottle neck in the realization of a system on chip in scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the output impedance (gain) and supply voltage which limits the dynamic range (output swing). One way to mitigate the power supply restrictions is to move to current mode circuit circuit design rather than voltage mode designs. This thesis focuses on designing Process Voltage and Temperature (PVT) tolerant base band circuits at lower supply voltages and in lower technologies. Inverter amplifiers are known to have better transconductance efficiency, better noise and linearity performance. But inverters are prone to PVT variations and has poor CMRR and PSRR. To circumvent the problem, we have proposed various biasing schemes for inverter like semi constant current biasing, constant current biasing and constant gm biasing. Each biasing technique has its own advantages, like semi constant current biasing allows to select different PMOS and NMOS current. This feature allows for higher inherent inverter linearity. Similarly constant current and constant gm biasing allows for reduced PVT sensitivity. The inverter based OTA achieves a measured THD of -90.6 dB, SNR of 78.7 dB, CMRR 97dB, PSRR 61 dB wile operating from a nominal power of 0.9V and at output swing of 0.9V{pp,diff} in TSMC 40nm general purpose process. Further the measured third harmonic distortion varies approximately by 11.5dB with 120C variation in temperature and 9dB with a 18% variation in supply voltage. The linearity can be increased by increasing the loop gain and bandwidth in a negative feedback circuit or by increasing the over drive voltage in open loop architectures. However both these techniques increases the noise contribution of the circuit. There exist a trade off between noise and linearity in analog circuits. To circumvent this problem, we have introduced nonlinear cancellation techniques and noise filtering techniques. An analog-to-digital converter (ADC) driver which is capable of amplifying the continuous time signal with a gain of 8 and sample onto the input capacitor(1pF) of 1 10 bit successive approximation register (SAR) ADC is designed in TSMC 65nm general purpose process. This exploits the non linearity cancellation in current mirror and also allows for higher bandwidth operation by decoupling closed loop gain from the negative feedback loop. The noise from the out of band is filtered before sampling leading to low noise operation. The measured design operates at 100MS/s and has an OIP_3 of 40dBm at the nyquist rate, noise power spectral density of 17nV/sqrt{Hz} and inter modulation distortion of 65dB. The intermodulation distortion variation across 10 chips is 6dB and 4dB across a temperature variation of 120C. Non linearity cancellation is exploited in designing two filters, an anti alias filter and a continuously tunable channel select filter. Traditional active RC filters are based on cascade of integrators. These create multiple low impedance nodes in the circuit which results in a higher noise. We propose a real low pass filter based filter architecture rather than traditional integrator based approach. Further the entire filtering operation takes place in current domain to circumvent the power supply limitations. This also facilitates the use of tunable non linear metal oxide semiconductor capacitor (MOSCAP) as filter capacitors. We introduce techniques of self compensation to use the filter resistor and capacitor as compensation capacitor for lower power. The anti alias filter designed for 50MHz bandwidth is fabricated in IBM 65nm process achieves an IIP3 of 33dBm, while consuming 1.56mW from 1.2 V supply. The channel select filter is tunable from 34MHz to 314MHz and is fabricated in TSMC 65nm general purpose process. This filter achieves an OIP3 of 25.24 dBm at the maximum frequency while drawing 4.2mA from 1.1V supply. The measured intermodulation distortion varies by 5dB across 120C variation in temperature and 6.5dB across a 200mV variation in power supply. Further this filter presents a high impedance node at the input and a low impedance node at the output easing system integration. SAR ADCs are becoming popular at lower technologies as they are based on device switching rather than amplifying circuits. But recent SAR ADCs that have good energy efficiency have had relatively large input capacitance increasing the driver power. We present a 2X time interleaved (TI) SAR ADC which has the lowest input capacitance of 133fF in literature. The sampling capacitor is separated from the capacitive digital to analog converter (DAC) array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in charge domain. The proposed ADC is fabricated in TSMC's 65nm general purpose process and occupies an area of 0.0338 mm^2. The measured ADC spurious free dynamic range (SFDR) is 57dB and the measured effective number of bits (ENOB) at nyquist rate is 7.55 bit while using 1.55mW power from 1 V supply. A sub 1V reference circuit is proposed, that exploits the complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Chopper stabilization is employed to reduce the flicker noise of the reference circuit. The prototype was simulated in TSMC 65nm process and we obtain the nominal output of 236mW, while consuming 0.7mW from power supply. Simulations show a temperature coefficient of 18 ppmC from -40 to 100C and with a power supply ranging from 0.8 to 2V

Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance