Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Low power VLSI design of a fir filter using dual edge triggered clocking strategy

Digital signal processing is an area of science and engineering that has developed rapidly over the past 30 years. This rapid development is a result of the significant advances in digital computer technology and integrated–circuit fabrication. DSP processors are a diverse group, most share some common features designed to support fast execution of the repetitive, numerically intensive computations characteristic of digital signal processing algorithms. The most often cited of these features is the ability to perform a multiply-accumulate operation (often called a "MAC") in a single instruction cycle. Hence in this project a DSP Processor is designed which can perform the basic DSP Operations like convolution, fourier transform and filtering. The processor designed is a simple 4-bit processor which has single data line of 8-bits and a single address bus of 16-bits. With a set of branch instructions the project DSP will operate as a CISC processor with strong math capabilities and can perform the above mentioned DSP operations. The application I have taken is the low power FIR filter using dual edge clocking strategy. It combines two novel techniques for the power reduction which is : multi stage clock gating and a symmetric two-phase level-sensitive clocking with glitch aware re-distribution of data-path registers. Simulation results confirm a 42% reduction in power over single edge triggered clocking with clock gating.Also to further reduce the power consumption the a low power latch circuit is used. Thanks to a partial pass-transistor logic, it trades time for energy, being particularly suitable for low power low-frequency applications. Simulation results confirm the power reduction. This technique discussed can be implemented to portable devices which needs longer battery life and to ASIC’

Reducing energy with asynchronous circuits

Reducing energy consumption using asynchronous circuits. The elastic clocks approach has been implemented along with a closed-feedback loop in order to achieve a lower energy consumption along with more reliability in integrated circuits

High-Accuracy Digital to Analog Converter Dedicated to Sine-Waveform Generator for Avionic Applications

RÉSUMÉ De nos jours, malgré les avancées remarquables de la microélectronique, les systèmes avioniques emploient essentiellement des technologies vieillissantes afin de répondre aux normes de sécurité exigeantes des systèmes avioniques. La nouvelle génération d'avionique modulaire intégrée (AMI) des More Electric Aircrafts (MEA), nécessite des architectures de réseaux stables et fiables, employant des modules électroniques intégrables modernes qui restent à être conçus et développés. Suivant cette tendance, une interface générique intelligente pour capteurs (Smart Sensor Interface - SSI), dédiée aux capteurs de position avionique est proposée dans ce mémoire. Le circuit intégré SSI fera partie d'un réseau de capteurs AFDX amélioré et est composé de signaux d'excitation et de modules d'acquisition de données. Les efforts de conception sont concentrés sur l'unité de génération de signaux d'excitation (Excitation Signal Generation - ESG) de la SSI. En tant que lien entre le réseau AFDX et les capteurs de déplacement, l'unité ESG doit générer des signaux sinusoïdaux précis, d'une fréquence allant de 1.5 kHz à 10 kHz. En respectant la programmation de l'interface, nous démontrerons qu'une architecture de générateur de signaux basée sur la mémoire est la seule option qui réponde aux objectifs du design. Le design d'un convertisseur numérique-analogique (CNA) basé sur le principe du sur-échantillonnage et faisant partie du chemin ESG est également présenté dans ce travail. Ce CNA est le noyau d'un générateur de signaux sinusoïdaux versatile conçu pour le système SSI proposé. Un taux d'échantillonnage élevé est utilisé dans ce CNA, de façon à obtenir un rapport signal sur bruit (Signal to Noise Ratio - SNR) élevé. Une analyse de l'impact d'une implémentation carrée et non-carrée de la matrice de sources de courant (Current Source Array - CSA) sur la performance de la séquence de commutation est présentée. Il sera démontré que la considération de tels impacts conduit à la conception de CNA plus précis. Une séquence de commutation optimale pour la taille du CSA conçu, sera introduite. Afin de réduire la taille des plots d'entrées et de sorties de la puce, un convertisseur de données série à parallèle haute-vitesse est inclu dans le CNA. Ainsi, les données d'entrée peuvent être envoyées de façon sérielle à un registre à décalage et appliquées de façon interne au noyau du CNA.----------ABSTRACT Today, despite the astonishing advances in the field of Microelectronics, avionics systems are mostly employing older technologies to guarantee the level of reliability required by stringent safety standards of avionic systems. Toward the new generation of Integrated Modular Avionics (IMA) in More Electric Aircrafts (MEA), reliable and stable network architecture which employs modern integrated electronic modules must be designed and developed. In this trend, a generic Smart Sensor Interface (SSI) for avionics displacement sensors will be proposed in this Master thesis. The integrated SSI circuit will be part of an improved AFDX sensor network and consists of signal excitation and data acquisition paths. The design efforts of this Master thesis will focus on the Excitation Signal Generation (ESG) unit of the SSI. As a link between AFDX network and displacement sensors, the ESG unit should generate pure and accurate sine-waveform with variable frequency between 1.5 kHz and 10 kHz. Respecting the programmability of the interface, it will be shown that a memory-based signal generator architecture is the only choice which supports the design objectives. As part of the ESG path, the detailed design of a 10-bit interpolating digital to analog converter (DAC) will also be presented in this work. The DAC is the core of a versatile sine-waveform generator unit designed for avionics SSI. High-speed sample rate will be used in this segmented current steering DAC in order to achieve a high Signal to Noise Ratio (SNR). In the module level design of the DAC, the impact of square and non-square implementation of the current source array (CSA) on the performance of the switching sequence is introduced. It will be shown that considering such impacts will lead to the design of more accurate DACs. An optimum switching sequence for the designed CSA size will be designed and introduced. In order to reduce the I/O pads of the chip, high-speed serial to parallel converter will be included in the DAC. Thus the input data can be serially sent to the input shift register and internally applied to the DAC core. The DAC was fabricated on 1.2 × 1.2 mm2 chip fabricated using IBM 0.13µm CMOS technology, operating with a supply voltage of 1.2 V. Sourcing a sine wave current with a peak of 1023 µA, the proposed DAC is able to achieve a SNR better than 84 dB in the Nyquist bandwidth of DC to 20 kHz

Design, scale-up and characterization of the data acquisition system for the ANAIS dark matter experiment

El proyecto ANAIS, iniciado en los noventa, se ha dedicado a desarrollar un experimento de materia oscura con ioduro de sodio en el Laboratorio Subterráneo de Canfranc (LSC) y podría confirmar el resultado positivo de DAMA/LIBRA usando la misma técnica y el mismo material blanco. Un experimento de estas características posee unos requisitos muy estrictos para tener sensibilidad suficiente a la modulación anual: tener el menor fondo radioactivo posible en la zona de interés, poseer un umbral energético muy bajo y tener suficiente masa. Además de estos requisitos fundamentales es necesaria una muy buena estabilidad en la adquisición de datos y un buen control de los parámetros ambientales para evitar que posibles efectos sistemáticos puedan ser tomados por modulación anual de materia oscura. El experimento ANAIS constará de más de cien kilogramos de ioduro de sodio ultrapuro en proceso de fabricación y que serán instalados en los próximos meses en el LSC. Esta tesis ha estado enfocada al diseño, implementación y caracterización de un sistema de adquisición de datos adecuado para el experimento ANAIS teniendo en cuenta los requisitos antes mencionados. Se han estudiado los fotomultiplicadores (PMTs) elegidos para la detección de la luz del centelleo del ioduro de sodio. Además se han desarrollado los algoritmos y protocolos necesarios para hacer el control de calidad de todas la unidades. Se ha descrito el diseño de la electrónica necesaria para la adquisición de datos de los módulos de ioduro y los centelladores plásticos usados como detector de muones junto con el software de adquisición y de análisis de datos. También se ha medido la recogida de luz de tres módulos de Alpha Spectra, los dos primeros de que constó el prototipo ANAIS-25 y un tercero que unido a los dos anteriores formaron ANAIS-37. Por último, se ha hecho un estudio de la estabilidad de los parámetros ambientales y de parámetros cruciales para la adquisición de datos.The ANAIS project has been a long time effort devoted to carry out an experiment to detect dark matter annual modulation with very low background NaI(Tl) detectors. This experiment could confirm the DAMA/LIBRA positive signal with the same target and technique. Such an experiment has a very stringent requirements in order to have enough sensitivity to an annual modulation at very low energy. These requirements are: very low energy threshold, a background as low as possible in the region of interest and a high enough target mass. In addition to these fundamental requirements, very good stability and control of environmental parameters have to be accomplished in order to avoid systematic effects to mimic the effect of the annual modulation. An experiment of more than one hundred kilograms of ultrapure NaI(Tl) has been conceived and it is being commissioned at the Canfranc Underground Laboratory (LSC). This work was devoted to the design, implementation and characterization of a data acquisition system suitable for the ANAIS experiment, having in mind the previously mentioned requirements. It has described the Photomultiplier Tubes (PMTs) used by the ANAIS modules and the algorithms and protocol developed in order to pass quality tests to all units. It has presented the design and implementation of the electronic front-end for the ANAIS modules and muon tagging system along with the data acquisition software. The analysis software was adapted from the software of the previous prototypes to allow easy scale-up to the full experiment. Finally, the test of the optical performance of the Alpha Spectra modules and the tests of data acquisition and monitoring of environmental parameters were performed

Novel Front-end Electronics for Time Projection Chamber Detectors

Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET). En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso. La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia. El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible). Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC. Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reduccióGarcía García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980Palanci

Radio frequency interference detection and mitigation techniques for navigation and Earth observation

Radio-Frequency Interference (RFI) signals are undesired signals that degrade or disrupt the performance of a wireless receiver. RFI signals can be troublesome for any receiver, but they are especially threatening for applications that use very low power signals. This is the case of applications that rely on the Global Navigation Satellite Systems (GNSS), or passive microwave remote sensing applications such as Microwave Radiometry (MWR) and GNSS-Reflectometry (GNSS-R). In order to solve the problem of RFI, RFI-countermeasures are under development. This PhD thesis is devoted to the design, implementation and test of innovative RFI-countermeasures in the fields of MWR and GNSS. In the part devoted to RFI-countermeasures for MWR applications, first, this PhD thesis completes the development of the MERITXELL instrument. The MERITXELL is a multi-frequency total-power radiometer conceived to be an outstanding platform to perform detection, characterization, and localization of RFI signals at the most common MWR imaging bands up to 92 GHz. Moreover, a novel RFI mitigation technique is proposed for MWR: the Multiresolution Fourier Transform (MFT). An assessment of the performance of the MFT has been carried out by comparison with other time-frequency mitigation techniques. According to the results, the MFT technique is a good trade-off solution among all other techniques since it can mitigate efficiently all kinds of RFI signals under evaluation. In the part devoted to RFI-countermeasures for GNSS and GNSS-R applications, first, a system for RFI detection and localization at GNSS bands is proposed. This system is able to detect RFI signals at the L1 band with a sensitivity of -108 dBm at full-band, and of -135 dBm for continuous wave and chirp-like signals when using the averaged spectrum technique. Besides, the Generalized Spectral Separation Coefficient (GSSC) is proposed as a figure of merit to evaluate the Signal-to-Noise Ratio (SNR) degradation in the Delay-Doppler Maps (DDMs) due to the external RFI effect. Furthermore, the FENIX system has been conceived as an innovative system for RFI detection and mitigation and anti-jamming for GNSS and GNSS-R applications. FENIX uses the MFT blanking as a pre-correlation excision tool to perform the mitigation. In addition, FENIX has been designed to be cross-GNSS compatible and RFI-independent. The principles of operation of the MFT blanking algorithm are assessed and compared with other techniques for GNSS signals. Its performance as a mitigation tool is proven using GNSS-R data samples from a real airborne campaign. After that, the main building blocks of the patented architecture of FENIX have been described. The FENIX architecture has been implemented in three real-time prototypes. Moreover, a simulator named FENIX-Sim allows for testing its performance under different jamming scenarios. The real-time performance of FENIX prototype has been tested using different setups. First, a customized VNA has been built in order to measure the transfer function of FENIX in the presence of several representative RFI/jamming signals. The results show how the power transfer function adapts itself to mitigate the RFI/jamming signal. Moreover, several real-time tests with GNSS receivers have been performed using GPS L1 C/A, GPS L2C, and Galileo E1OS. The results show that FENIX provides an extra resilience against RFI and jamming signals up to 30 dB. Furthermore, FENIX is tested using a real GNSS timing setup. Under nominal conditions, when no RFI/jamming signal is present, a small additional jitter on the order of 2-4 ns is introduced in the system. Besides, a maximum bias of 45 ns has been measured under strong jamming conditions (-30 dBm), which is acceptable for current timing systems requiring accuracy levels of 100 ns. Finally, the design of a backup system for GNSS in tracking applications that require high reliability against RFI and jamming attacks is proposed.Les interferències de radiofreqüència (RFI) són senyals no desitjades que degraden o interrompen el funcionament dels receptors sense fils. Les RFI poden suposar un problema per qualsevol receptor, però són especialment amenaçadores per les a aplicacions que fan servir senyals de molt baixa potència. Aquest és el cas de les aplicacions que depenen dels sistemes mundials de navegació per satèl·lit (GNSS) o de les aplicacions de teledetecció passiva de microones, com la radiometria de microones (MWR) i la reflectometria GNSS (GNSS-R). Per combatre aquest problema, sistemes anti-RFI s'estan desenvolupament actualment. Aquesta tesi doctoral està dedicada al disseny, la implementació i el test de sistemes anti-RFI innovadors en els camps de MWR i GNSS. A la part dedicada als sistemes anti-RFI en MWR, aquesta tesi doctoral completa el desenvolupament de l'instrument MERITXELL. El MERITXELL és un radiòmetre multifreqüència concebut com una plataforma excepcional per la detecció, caracterització i localització de RFI a les bandes de MWR més utilitzades per sota dels 92 GHz. A més a més, es proposa una nova tècnica de mitigació de RFI per MWR: la Transformada de Fourier amb Multiresolució (MFT). El funcionament de la MFT s'ha comparat amb el d'altres tècniques de mitigació en els dominis del temps i la freqüència. D'acord amb els resultats obtinguts, la MFT és una bona solució de compromís entre les altres tècniques, ja que pot mitigar de manera eficient tots els tipus de senyals RFI considerats. A la part dedicada als sistemes anti-RFI en GNSS i GNSS-R, primer es proposa un sistema per a la detecció i localització de RFI a les bandes GNSS. Aquest sistema és capaç de detectar senyals RFI a la banda L1 amb una sensibilitat de -108 dBm a tota la banda, i de -135 dBm per a senyals d'ona contínua i chirp fen un mitjana de l'espectre. A més a més, el Coeficient de Separació Espectral Generalitzada (GSSC) es proposa com una mesura per avaluar la degradació de la relació senyal a soroll (SNR) en els Mapes de Delay-Doppler (DDM) a causa del impacte de les RFI. La major contribució d'aquesta tesi doctoral és el sistema FENIX. FENIX és un sistema innovador de detecció i mitigació de RFI i inhibidors de freqüència per aplicacions GNSS i GNSS-R. FENIX utilitza la MFT per eliminar la interferència abans del procés de correlació amb el codi GNSS independentment del tipus de RFI. L'algoritme de mitigació de FENIX s'ha avaluat i comparat amb altres tècniques i els principals components de la seva arquitectura patentada es descriuen. Finalment, un simulador anomenat FENIX-Sim permet avaluar el seu rendiment en diferents escenaris d'interferència. El funcionament en temps real del prototip FENIX ha estat provat utilitzant diferents mètodes. En primer lloc, s'ha creat un analitzador de xarxes per a mesurar la funció de transferència del FENIX en presència de diverses RFI representatives. Els resultats mostren com la funció de transferència s'adapta per mitigar el senyal interferent. A més a més, s'han realitzat diferents proves en temps real amb receptors GNSS compatibles amb els senyals GPS L1 C/A, GPS L2C i Galileo E1OS. Els resultats mostren que FENIX proporciona una resistència addicional contra les RFI i els senyals dels inhibidors de freqüència de fins a 30 dB. A més a més, FENIX s'ha provat amb un sistema comercial de temporització basat en GNSS. En condicions nominals, sense RFI, FENIX introdueix un petit error addicional de tan sols 2-4 ns. Per contra, el biaix màxim mesurat en condicions d'alta interferència (-30 dBm) és de 45 ns, el qual és acceptable per als sistemes de temporització actuals que requereixen nivells de precisió d'uns 100 ns. Finalment, es proposa el disseny d'un sistema robust de seguiment, complementari als GNSS, per a aplicacions que requereixen alta fiabilitat contra RFI.Postprint (published version

Traffic Analysis of Anonymity Systems

This research applies statistical methods in pattern recognition to test the privacy capabilities of a very popular anonymity tool used on the Internet known as Tor. Using a recently developed algorithm known as Causal State Splitting and Reconstruction (CSSR), we can create hidden Markov models of network processes proxied through Tor. In contrast to other techniques, our CSSR extensions create a minimum entropy model without any prior knowledge of the underlying state structure. The inter-packet time delays of the network process, preserved by Tor, can be symbolized into ranges and used to construct the models. After the construction of training models, detection is performed using Confidence Intervals. New test data can be fed through a model to determine the intervals and estimate how well the data matches the model. If a match is found, the state sequence, or path, can be used to uniquely describe the data with respect to the model. It is by comparing these paths that Tor users can be identified. Packet data from any two computers using the Tor network can be matched to a model and their state sequences can be compared to give a statistical likelihood that the two systems are actually communicating together over Tor. We perform experiments on a private Tor network to validate this. Results showed that communicating systems could be identified with a 95% accuracy in our test scenario. This attack differs from previous maximum likelihood-based approaches in that it can be performed between just two computers using Tor. The adversary does not need to be a global observer. The attack can also be performed in real-time provided that a matching model had already been constructed