Development of a Universal MOSFET Gate Impedance Model

Scaling of CMOS technology to 100 nm & below and the endless pursuit of higher operating frequencies drive the need to accurately model effects that dominate at those feature sizes and frequencies. Current modeling techniques are frequency limited and require different models for different frequency ranges in order to achieve accuracy goals. In the foundry world, high frequency models are typically empirical in nature and significantly lag their low frequency counterparts in terms of availability. This tends to slow the adoption of new foundry technologies for high performance applications such as extremely high data rate serializer/deserializer transceiver cores. However, design cycle time and time to market while transitioning between technology nodes can be reduced by incorporating a reusable, industry-standard model. This work proposes such a model for device gate impedance that is simulator-friendly, compact, frequencyindependent, and relatively portable across technology nodes. This semi-empirical gate impedance model is based on depletion in the poly-silicon gate electrode. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 110 nm and 180 nm technologies in the 1-20GHz frequency range. The measured data illustrates that the device input impedance has a non-linear frequency dependency. This variation in input impedance is the result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region for 1-20GHz frequency range. The gate impedance model is further modified by incorporating parasitic effects, extending its range to 200MHz-20GHz. This model performs accurately for 180 run, 110 nm and 90 nm technologies at different bias conditions and dimensions. The model and model parameter behavior are consistent across technology nodes thereby enabling re-usability and portability. The accuracy of this new gate impedance model is demonstrated in various applications: to validate the model extraction techniques for different device configurations, to assess the input data run-length variations on CML buffer performance and to estimate the jitter in ring oscillators

Application of Graphene within Optoelectronic Devices and Transistors

Scientists are always yearning for new and exciting ways to unlock graphene's true potential. However, recent reports suggest this two-dimensional material may harbor some unique properties, making it a viable candidate for use in optoelectronic and semiconducting devices. Whereas on one hand, graphene is highly transparent due to its atomic thickness, the material does exhibit a strong interaction with photons. This has clear advantages over existing materials used in photonic devices such as Indium-based compounds. Moreover, the material can be used to 'trap' light and alter the incident wavelength, forming the basis of the plasmonic devices. We also highlight upon graphene's nonlinear optical response to an applied electric field, and the phenomenon of saturable absorption. Within the context of logical devices, graphene has no discernible band-gap. Therefore, generating one will be of utmost importance. Amongst many others, some existing methods to open this band-gap include chemical doping, deformation of the honeycomb structure, or the use of carbon nanotubes (CNTs). We shall also discuss various designs of transistors, including those which incorporate CNTs, and others which exploit the idea of quantum tunneling. A key advantage of the CNT transistor is that ballistic transport occurs throughout the CNT channel, with short channel effects being minimized. We shall also discuss recent developments of the graphene tunneling transistor, with emphasis being placed upon its operational mechanism. Finally, we provide perspective for incorporating graphene within high frequency devices, which do not require a pre-defined band-gap.Comment: Due to be published in "Current Topics in Applied Spectroscopy and the Science of Nanomaterials" - Springer (Fall 2014). (17 pages, 19 figures

CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip

Quantum computing is experiencing the transition from a scientific to an engineering field with the promise to revolutionize an extensive range of applications demanding high-performance computing. Many implementation approaches have been pursued for quantum computing systems, where currently the main streams can be identified based on superconducting, photonic, trapped-ion, and semiconductor qubits. Semiconductor-based quantum computing, specifically using CMOS technologies, is promising as it provides potential for the integration of qubits with their control and readout circuits on a single chip. This paves the way for the realization of a large-scale quantum computing system for solving practical problems. In this paper, we present an overview and future perspective of CMOS quantum computing, exploring developed semiconductor qubit structures, quantum gates, as well as control and readout circuits, with a focus on the promises and challenges of CMOS implementation

Novel modelling methods for microwave GaAs MESFET device

Ph.DDOCTOR OF PHILOSOPH

Electron – phonon interaction in multiple channel GaN based HFETs: Heat management optimization

New power applications for managing increasingly higher power levels require that more heat be removed from the power transistor channel. Conventional treatments for heat dissipation do not take into account the conversion of excess electron energy into longitudinal optical (LO) phonons, whose associated heat is stored in the channel unless such LO phonons decay into longitudinal acoustic (LA) phonons via a Ridley path. A two dimensional electron gas (2DEG) density of ~5×1012cm-2 in the channel results in a strong plasmon–LO phonon coupling (resonance) and a minimum LO phonon lifetime is experimentally observed, implying fast heat removal from the channel. Therefore, it is desirable to shift the resonance condition to higher 2DEG densities, and thereby higher power levels. The more convenient way to attain the latter is by widening the 2DEG density profile via heterostructure engineering, i.e. by using multiple channel heterostructures. A single channel heterostructure (GaN/AlN/AlGaN), a basic heterostructure used to obtain a 2DEG, exhibits a resonance condition at low 2DEG densities (~0.65×1012 cm-2). Successful widening of the 2DEG density xv profile was predicted by simulation results for two types of multiple (Al)GaN channel heterostructures, i.e. coupled channel GaN/AlN/GaN/AlN/AlGaN and dual channel GaN/AlGaN/AlN/AlGaN. Because of a reduction of carrier confinement, it is experimentally observed that control of the channel is moderate in the case of dual channel heterostructures. On the other hand, carrier confinement provides a better control of the channel in coupled channel heterostructures. Furthermore, unlike in a dual channel heterostructure, alloy scattering does not affect carrier transport properties, which results in a higher cut-off frequency. It was found experimentally that the coupled channel heterostructure successfully reaches resonance condition at a 2DEG density that is 23% higher than in a single channel heterostructure. Multiple channel heterostructures therefore provide a convenient way to shift the plasmon-LO phonon resonance to higher 2DEG densities. However, in our grown heterostructures, high power levels under optimal channel working conditions and minimum heat accumulation, all desirable benefits for the development of high power transistors, were only observed in coupled channel heterostructures

Development of 20 GHz monolithic transmit modules

The history of the development of a transmit module for the band 17.7 to 20.2 GHz is presented. The module was to monolithically combine, on one chip, five bits of phase shift, a buffer amplifier and a power amplifier to produce 200 mW to the antenna element. The approach taken was MESFET ion implanted device technology. A common pinch-off voltage was decided upon for each application. The beginning of the total integration phases revealed hitherto unencountered hazards of large microwave circuit integration which were successfully overcome. Yield and customer considerations finally led to two separate chips, one containing the power amplifiers and the other containing the complete five bit phase shifter

Analysis & Design of Non-Linear Amplifiers for Efficient Microwave Transmitters

This thesis addresses analysis and design of high efficiency microwave power amplifiers and rectifiers. The focus of this body of work is to optimize narrow band power amplifiers for maximization of Power-Added-Efficiency (PAE) and rectifiers for maximization of RF-DC power conversion efficiency. A power amplifier performs DC-RF conversion while a rectifier performs RF-DC conversion, therefore a strong analogy exists between the two. Design with non-linear devices suffers from lack of accurate models characterizing large signal behavior, therefore measurement based techniques are often adopted in order to create high performance designs. The theoretical analysis presented in this thesis provides the microwave circuit designer intuition concerning performance expectations of design options rather than a recipe for creating a successful design. The complexity of non-linear device physics results in behavior which is often limited to qualitative description, complicating accurate model development. The presented theoretical analysis is applied to load-pull based design of S-Band and X-Band power amplifiers and S-Band power rectifiers. The measured circuits exhibit high efficiency consistent with the analysis. An implementation of a high efficiency pulsed S-band AM radar transmitter is presented along with measured results. An extension of the presented analysis is investigated in the form of a harmonic injection amplifier, which conceptually allows realization of a high power, high efficiency broadband amplifier. In summary, this thesis details 1) the load-pull measurement based design technique applied to microwave power amplifiers and rectifiers, 2) a theoretical analysis technique characterizing the performance limitations of harmonically terminated power amplifiers which may be applied to power rectifiers as well, 3) the design and measurement of several successful high efficiency power amplifiers and rectifiers and 4) interesting implementations of the presented theory in a system context