Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

Baseband processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

Commissioning and Operation of the New CMS Phase-1 Pixel Detector

The Phase-1 upgrade of the CMS pixel detector is built out of four barrel layers (BPix) and three forward disks in each endcap (FPix). It comprises a total of 124M pixel channels in 1,856 modules, and it is designed to withstand instantaneous luminosities of up to $2 \times 10^{34}\,$cm$^{-2}$s$^{-1}$. Different parts of the detector were assembled over the last year and later brought to CERN for installation inside the CMS tracker. At various stages during the assembly tests have been performed to ensure that the readout and power electronics and the cooling system meet the design specifications. After tests of the individual components, system tests were performed before the installation inside CMS. In addition to reviewing these tests, we also present results from the final commissioning of the detector in-situ using the central CMS DAQ system. Finally we review results from the initial operation of the detector first with cosmic rays and then with pp collisions.Comment: Talk presented at the APS Division of Particles and Fields Meeting (DPF 2017), July 31-August 4, 2017, Fermilab. C17073

The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Content addressable memory project

A parameterized version of the tree processor was designed and tested (by simulation). The leaf processor design is 90 percent complete. We expect to complete and test a combination of tree and leaf cell designs in the next period. Work is proceeding on algorithms for the computer aided manufacturing (CAM), and once the design is complete we will begin simulating algorithms for large problems. The following topics are covered: (1) the practical implementation of content addressable memory; (2) design of a LEAF cell for the Rutgers CAM architecture; (3) a circuit design tool user's manual; and (4) design and analysis of efficient hierarchical interconnection networks

Despliegue de red LPWAN en entorno industrial con movilidad

[ES] La tecnología que comenzó a conectar masivamente a las personas hace décadas se ha desarrollado para conectar dispositivos también. La red de conectividad global resultante se denomina el internet de las cosas. Tiene aplicaciones útiles en todos los sectores de la economía y está preparado para liderar la cuarta revolución industrial, que busca la eficiencia a través de la recopilación de datos. Para lograrlo se necesita un número cada vez mayor de dispositivos, que deben ser eficientes energéticamente para permitir que estas redes sean viables tanto económica como ambientalmente. Cubrir grandes espacios con la menor cantidad posible de recursos de hardware también ayuda a reducir los costes de despliegue, y aquí es exactamente donde entran en juego las redes LPWAN (Low-Power Wide-Area Network). El objetivo de este proyecto es crear una herramienta que permita el despliegue rápido y sencillo de una red LPWAN en un entorno industrial en un contexto de movilidad. El autor ha seleccionado la tecnología LPWAN que mejor se adapta al proyecto (LoRaWAN) y una solución basada en ella, ChirpStack. Se ha desarrollado una aplicación web funcional como candidata ideal para ser la herramienta que permita despliegues de movilidad LPWAN. El uso de la aplicación web desarrollada conlleva además una mayor eficiencia de costes, ya que ahorra al usuario múltiples pasos de configuración tediosos antes de activar un nuevo nodo. Esta herramienta también logra una mayor abstracción de la tecnología de comunicaciones que se está implementando, haciéndola accesible a un mercado aún mayor. Un análisis de los resultados obtenidos destaca el éxito en la consecución de dos objetivos secundarios, la reducción del tiempo de activación del dispositivo final y la abstracción de la tecnología adyacente, además de ser una herramienta de movilidad válida para el despliegue industrial de redes LPWAN.[EN] The technology that started massively connecting people decades ago has been developed to begin connecting devices as well. The resulting global connectivity network is called the Internet of Things. It has useful applications in every sector and is set to lead the fourth industrial revolution. Efficiency through data gathering is the goal of an ever-increasing number of devices. Energy efficiency is key to make this network scalable without skyrocketing electrical consumption. Covering big spaces with as few hardware resources as possible also helps at reducing costs. This is exactly where Low-Power Wide-Area Networks come into play. The aim of this project is to create a tool that allows the fast and easy deployment of a LPWAN network in an industrial environment in a mobility context. The author has selected the LPWAN technology that best fits the project (LoRaWAN) and a solution based on it, ChirpStack. A functional web application has been developed as an ideal candidate to be the tool that allows LPWAN mobility deployments. Further cost efficiency is unlocked by the developed web application, which saves the user multiple tedious configuration steps before activating a new end-device. This tool also achieves further abstraction from the technology that is being implementing, making it accessible to an even greater market. An analysis of the results obtained highlights the success in achieving both secondary goals, a reduction in end-device activation time and an abstraction of the telecommunications technology, apart from being a mobility tool for industrial deployment of LPWAN networks.Hernández Álvarez, R. (2022). Despliegue de red LPWAN en entorno industrial con movilidad. Universitat Politècnica de València. http://hdl.handle.net/10251/181897TFG